The K8 is here to stay

One of the most interesting points that we came away from our discussion of future AMD architectures was Weber's stance that the K8 execution core is as wide as they are going to go for quite some time.  Remember that the K8 execution core was taken from the K7, so it looks like the execution core that was originally introduced in the first Athlon will be with us even after the Athlon 64. 

What's even more interesting is that Intel's strategy appears to confirm that AMD's decision was indeed the right one. After all, it looks like the Pentium M architecture is eventually going to be adapted for the desktop in the coming years.  Based on the P6 execution core, the Pentium M is inherently quite similar (although also inferior) to the K7/K8 execution core that AMD has developed.  Given that Intel is slowly but surely implementing architectural features that AMD has done over the past few years, we wouldn't be too shocked to see an updated Pentium M execution core that was more competitive with the K7/K8 by the time that the Pentium M hits the desktop. 

Fred went on to say that for future microprocessors, he's not sure if the K8 core necessarily disappears and that in the long run, it could be that future microprocessors feature one or more K8 cores complemented by other cores.  Weber's comments outline a fundamental shift in the way that microprocessor generations are looked at.  In the past, the advent of a new microprocessor architecture meant that the outgoing architecture was retired - but now it looks as if outgoing architectures will be incorporated and complemented rather than put out to pasture.  The reason for this reuse instead of retire approach is simple - with less of a focus on increasing ILP, the role of optimizing the individual core decreases, and the problems turn into things like: how many cores can you stick on a die and what sort of resources do they share? 

In the past, new microprocessor architectures were sort of decoupled from new manufacturing processes.  You'd generally see a new architecture debut on whatever manufacturing process was out at the time and eventually scale down to smaller and smaller processes, allowing for more features (i.e. cache) and higher clock speeds.  In the era of multi-core, its the manufacturing process that really determines how many cores you can fit on a die and thus, the introduction of "new architectures" is very tightly coupled with smaller manufacturing processes.  We put new architectures in quotes because often times, the architectures won't be all that different on an individual core basis, but as an aggregate, we may see significant changes. 

How about a Hyper Threaded Athlon?

When Intel announced Hyper Threading, AMD wasn't (publicly) paying any attention at all to TLP as a means to increase overall performance.  But now that AMD is much more interested and more public about their TLP direction, we wondered if there was any room for SMT a la Hyper Threading in future AMD processors, potentially working within multi-core designs. 

Fred's response to this question was thankfully straightforward; he isn't a fan of Intel's Hyper Threading in the sense that the entire pipeline is shared between multiple threads. In Fred's words, "it's a misuse of resources."  However, Weber did mention that there's interest in sharing parts of multiple cores, such as two cores sharing a FPU to improve efficiency and reduce design complexity.  But things like sharing simple units just didn't make sense in Weber's world, and given the architecture with which he's working, we tend to agree. 

Weber’s Thoughts on Cell An Update on Turion and Final Words


View All Comments

  • ceefka - Sunday, April 3, 2005 - link

    I assume this wafer and die stacking will also be used for increasing the GB's per RAM-stick. What else when 64-bit OSs and apps have become the standard? Is there any word from memory manufacturers on that? Reply
  • Athlex - Saturday, April 2, 2005 - link

    AMD seems to be missing the point of pitting Turion against Centrino. Intel's Centrino package requires a P-M, Intel chipset, and Intel wireless. Since most people don't know the diff between P-M and Centrino it's a brilliant way for Intel to move more silicon.

    Also confusing why AMD is using the same packaging for Turion CPUs as they do for normal A64 CPUs. The lowest-power XP-Ms use the smaller socket 563 (Sharp and Averatec systems for example). AMD already has a spec for a smaller 'socket 638' A64, seems like that should be the thin and light version.. C'mon AMD, let's see a real thin and light K8 notebook!
  • suryad - Friday, April 1, 2005 - link

    I agree...I cant wait for a dual core FX proc with each core clocked @ 3 GHz...think what a monster system that would be...yikes!! Reply
  • ceefka - Friday, April 1, 2005 - link

    #23 What exactly is ILP/TLP ?

    ILP Instruction Level Parallism
    TLP Thread Level Parallism

    It is explained in one of the CPU articles here on AT.

    Happy surfing.
  • BlvdKing - Friday, April 1, 2005 - link

    #26 - I would be torn between an IBM notebook and Turion too. IBM notebooks are amazing - full of features and so durable. Reply
  • cryptonomicon - Thursday, March 31, 2005 - link

    incredibly interesting article by anand.

    it seems like this is the kind of stuff you can only find at anantech.. the info is so in depth right from the source.
  • Regs - Thursday, March 31, 2005 - link

    Thank's Anand. With all this Intel news running about, it's good to see AMD isn't just planning to be a bench warmer. Reply
  • Xunilla - Thursday, March 31, 2005 - link

    #25 -- I agree, that is making a generalization that doesn't necessarily apply across the board. Reply
  • Xunilla - Thursday, March 31, 2005 - link

  • phaxmohdem - Thursday, March 31, 2005 - link

    I really want to see what kind of Turion notebooks spring forth. It will take a lot though to change my decision on the IBM T42 as my next notebook though. Reply

Log in

Don't have an account? Sign up now