Epox MVP3C-M MVP3 Super7 Boardby Anand Lal Shimpi on April 28, 1998 2:19 PM EST
- Posted in
One of the manufacturers that did the original VP3 chipset from VIA justice last year was Epox, their P55-VP3 was easily a knock-out upon its release. The Easy Setting Single Jumper setup made the absence of Jumperless Configuration Utility less of a pain. This time around, Epox is armed with a new chipset, the VIA MVP3, a new Jumper Setup, and even more importantly...a working 100MHz bus speed setting. In essence, Epox has the world's first example of a Working Super7 Motherboard on their hands.
Anand Tech Report Card Rating
|AT (w/ AT & ATX P/S Connectors)
|60 / 66 / 75 / 83 / 100 MHz
|1.5x / 2.0x / 2.5x / 3.0x / 3.5x / 4.0x / 4.5x / 5.0x
|2.1v / 2.2v / 2.8v / 2.9v / 3.2v
|3 168pin DIMM Slots (EDO/SDRAM)
|1 AGP Slot
4 PCI Slots
3 ISA Slots (1 Shared / 1 Full Length)
|AWARD PnP BIOS
|Taking a look at the layout of the MVP3C-M board, Epox did
a tremendous job with the design of this AT form factor product. While managing to
keep the size of the board relatively small, Epox managed to fit 4 PCI slots, 3 ISA, and 1
AGP slot on the board in addition to the 3 DIMM slots for memory expansion. Two of
the PCI slots will accept full length cards due to the positioning of the CPU Socket, a
socket which accepts and supports all current Socket-7 processors, including the upcoming
From the looks of the chipset on the MVP3C-M, it would appear to the untrained eye that Epox's newest motherboard was nothing more than an excellent VP3 board, however upon closer inspection the VT82C598AT markings on the CPU to PCI bridge chip itself make it clear that this board means business, as it is a true Super7 motherboard based on the new VIA MVP3 chipset.
The 512KB of 5ns L2 cache on-board is provided through the use of one chip complementing the 8ns Tag RAM. Due to the size of the L2 Cache in combination with that of the Tag RAM, the cacheable memory area of the MVP3C-M is 128MB, twice that of Intel's TX chipset. Upon boot-up the standard Award BIOS found on the board makes this clear by listing the cacheable DRAM size after displaying your system configuration information.
Accented by the fairly thorough Epox manual, the MVP3C-M manages to make your initial introduction to the world of Epox products a pleasant one at the least, courtesy of their traditional "user friendly" features. At the top of this list is the newly revised Easy Setting Dual Jumper (ESDJ) CPU Setup which easily replaces the need for a Jumperless CPU Setup. Using a single jumper, especially the attractively colored green jumpers with elongated handles Epox provides for those "hard to reach areas," you can select the clock multiplier from a set ranging from 2.0x - 5.0x. Moving up the CPU Configuration Jumper Block on the board you can use another jumper to select the bus speed, ranging from 60 to a fully operational 100MHz setting.
One of the most highly anticipated features of the MVP3 chipset is the ability to run your SDRAM at a Bus Clock of 66MHz pseudo-synchronously while your CPU/L2 cache makes use of the 100MHz bus speed. This opens up the Super7 market to the low cost arena as well, allowing upgrade addicts to re-use their older SDRAM that may not be PC100 Compliant in newer motherboards while not limiting themselves to < 100MHz bus speeds. This setting is featured on the MVP3C-M, unfortunately due to the nature of the revision of the board tested by AnandTech (Revision 0.2) both the SDRAM and AGP clocks could not operate at 66MHz, rendering the AGP bus virtually inoperable at the 100MHz setting and rendering the system paralyzed if you attempt to make use of the pseudo-synchronous SDRAM clock which is derived from the AGP Clock. Epox has informed AnandTech that they have corrected this problem, so expect to see more from them in the coming weeks.
The quality of the MVP3C-M couldn't be better for a board of this caliber, not only does Epox package the board with the latest AGP Gart and VIA Bus Mastering Drivers but they also paid special attention to the engineering qualities of their newest pride and joy. Their attention to detail is represented by the rock-solid stability, especially when overclocked, and not to mention when using the previously unstable 100MHz bus speed. During the extensive testing that was performed with the MVP3C-M, the test system never once exhibited any sort of erratic behavior while operating under even the most extreme conditions, where most motherboards would crack under pressure, the MVP3C-M continued to function flawlessly
Naturally, the performance of this motherboard using the 100MHz Front Side Bus Frequency is unparalleled by anything out today, simply using the 100MHz bus (which worked fine on both Intel and AMD processors; the Cyrix 6x86MX tested was a MX-200+ which is notorious for not being an overclocker's chip, and therefore didn't make it to the lowest setting of 100 x 2.0) increases overall system performance by a factor of 8 - 13% in Business Applications and Games.
But before you get too excited, there are a few things that need to be fixed with the MVP3C-M before it makes its official release...let's take a look at those before making the final decision on this board.
Don't worry about the AT form factor this board is available in, within a couple weeks time AnandTech will be receiving the ATX version of this board with a full Megabyte of Level 2 cache, that will double the maximum cacheable memory limit of the board to 256MB.
The only real problem encountered with the MVP3C-M was the fact that the board would not divide the AGP Clock properly at 100MHz bus speeds, making the use of a PCI Video card almost required for stable operation. Luckily Epox has informed AnandTech that they are working on this and it will be fixed by the time the board is officially released. Also, the lack of "in-between" voltage settings separating the 2.2v from the 2.8v Vcore settings on the board make it difficult to break the 333MHz mark with the K6-300 (3.5 x 100 isn't stable enough, most likely due to the voltage). Other than that, Epox has a definite hit on their hands.