Multiple Front Side Buses; Coming to an Intel Server Near Youby Kristopher Kubicki on November 4, 2004 4:13 AM EST
- Posted in
Dissecting code names seems like a full time job for some of
us lately. Fortunately, a full time job pays for my schooling so here are the
breakdown of Intel's newest code names, and what they mean to us.
Hopefully you have kept up with the last few articles from Anand and Jarred concerning dual core product SKUs and general Intel roadmaps. Of course, processors are only half of Intel's business - core logic composes the less glamorous side of Intel. Although we have been talking about Glenwood and Lakeport for several months now, today we are going to look at Intel's new server chipsets, Blackford and Greencreek.
Greencreek (also known as Greencreek 2S - 2Socket) is slated as the Tumwater (E7525) replacement, while Blackford is the Lindenhurst (E7520) replacement. In short, the two chipsets are nearly identical with Blackford serving as the high end version of the platform. The large news here is Intel's push for dual front side buses. The latest Intel roadmaps thoroughly describe dual independent buses as:
"New 2S platform architecture for improved performance"
2S, of course, denotes 2 Sockets. With advances towards dual core processing, the idea of independent buses per socket probably indicates the best approach possible for Intel to de-saturate the front side bus. We already know that Twin Castle will utilize independent memory controllers, and with Greencreek/Blackford showing up soon after with dedicated paths to their memory controllers, we could see large boosts in memory IO. The roadmap indicates Twin Castle will utilize multiple buses in later revisions as well.
Aside from dual buses, the new processors incorporate some other features as well, the largest being fully buffered DIMMs (FBD or FB-DIMM). The Memory Forum actually has a very concise IDF presentation with the memory architecture explained here. The apparent problem with DDR2 DIMMs (particularly when there are 8 or more) is that the signal gets very dirty. FB-DIMM attempts to solve this by placing a memory buffer directly on the DIMM itself. FB-DIMM aims to replace registered DIMMs, although the significant complexity of FBD will surely make it extremely expensive.
Blackford/Greencreek also boast "enhanced storage controllers" (most likely SATA-II) and EM64T compatibility as well. Below we have a small cross section on various chipset names and the details we know about them.
- Blackford: Lindenhurst successor for the Dempsey dual core processor. EM64T. Dual Independent FSB. FB-DIMM Support. Scheduled for H1'06.
- Greencreek: Tumwater successor for the Dempsey dual core processor. Will utilize two sockets. EM64T. Dual Independent FSB. FB-DIMM Support. Scheduled for H1'06.
- Twin Castle: 4 Socket platform for Xeon MP. Utilizes a dedicated memory controller. Will probably support dual core processors with a future revision that supports multiple (or at least dual FSB). Scheduled for Q1'06.
- Alviso: Intel's 915P chipset for the next generation Centrino platform. Scheduled for Q1'05.
- Sonoma: Next generation Centrino platform including Alviso. Scheduled for Q1'05.
- Napa: Successor for Sonoma designed for dual core mobility processors. Adds DDR2-667. Scheduled for Q1'06.
- Lakeport: 915P successor, supports 1066FSB, more PCIe lanes and 667MHz DDR-2, AMT and more EIST revisions. Scheduled for Q2'05.
- Glenwood: 925XE successor. Supports everything Lakeport does but should also include ECC capability. Scheduled for launch with Lakeport.
- Tekoa: Intel's next generation gigabit Ethernet chipset for deployment with Intel core logic.
- Mukilteo: Uniprocessor workstation release for the Glenwood/Lakeport generation. Supports EM64T.
- ICH7: Next generation south bridge. Comes in several different versions including a "Raid" version, DH (Ditigal Home), DO (Digital Office), DE (Digital Enterprise) versions as well.
Recently we have seen motherboard manufacturers disclose Pentium M platforms for the desktop. As more and more people start adopting higher clocked Pentium Ms over Celerons and Pentium 4s, don't be surprised to hear a lot more people giving attention to all things Centrino.
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Peter - Monday, November 29, 2004 - linkIndependent CPU busses on the north bridge?
*yawns* This is hardly news.
Pentium III Serverworks "Champion HE" chipset let you combine twin north bridges so you'd end up with two CPU busses (and two RAM controllers, incidentally).
AMD Athlon MP architecture had twin CPU busses out of one (AMD 762) north bridge chip.
AMD 64 has taken the next step beyond that already, eliminating CPU FSB altogether by planting the RAM controller into the CPU.
IntelUser2000 - Saturday, November 27, 2004 - linkWell sorry your theory is crap. Only reason Prescott is slower than Northwood(slow being 2-3% average, which is insignificant) is because Prescott has higher L1 and L2 latency, otherwise Prescott would have been faster.
Ibrahimmhmd - Tuesday, November 16, 2004 - linkThe only reason Intel is exhausting their existing technologies is due to the Tejas screw up. If you still remember, Tejas is the pre-Cedarmill processor which was supposed to take over the ailing Prescott. Prescott had speed paths problems even at 2.0Ghz initially. So Intel knew hitting 4.0Ghz will remain a dream for quite some time. With Tejas cancelled in favour of the Centrino cores for the future, Intel had to start switching over to some marketing tricks to make sure we forget about the GHz rules "knowledge" Intel has, for as long as they have existed, instilled in all its users. Yes, that's when they came up with the model number crap. Think about it. It paves way for Intel's introduction of the dual-core processors apart from the higher IPC centrino cores - how do you tell 6-pack-joe a 5GHz part will perform SLOWER than a 3GHz part? Coz it's got dual-core? What's a core to Joe?
Anyway, back to the main topic. Since Prescott is practically slower than Northwood clock-to-clock cache-size-to-cache-size, Intel took the decision to market Prescott with a larger cache. Even with that, there're quite a lot of apps that suffered from the longer pipeline Prescott had (due to the attempt to bump up the frequency, as well as some thing else ;-P ). At that juncture, Intel knew they were in deepest shit they have ever been since the Pentium FP flaw. They knew they were definitely losing the performance crown to AMD. To try to keep up with them and show us that they're still a competent rival to AMD, they had to dig out their dusty designs, tweak them and sell as new products until their next generation processors comes out.
In the meantime, they'll continue selling their CPUs as if they're still diligently churning out new technologies. You believed the latest Intel processor you bought is using the latest technology don't you? Don't you just love marketing.
Anyway, that's just my theory. Feel free to comment.
ceefka - Monday, November 8, 2004 - link#13 This dedicated (non on-die) memory controller sounds like a system that is going to suffer from latencies between the components. There are too many. Isn't this also an expensive approach? Designing a mobo for this concept will not easy, will it?
If Intel still relies on big caches and doubles their FSB (DIB) I think they're exhausting one old technology after the other, while adopting less fortunate ones like DDR2. I still think/hope they've something big up their sleeve, but this is not it.
While Intel can top AMD on various benchmarks, it takes costly technology that seems to be at the very end of its potential. I'd still favour an AMD 939 CPU because of the potential.
sprockkets - Sunday, November 7, 2004 - linkHmmm... perhaps a memory controller and then a PCI express controller, then a sb with all the usual stuff?
IntelUser2000 - Saturday, November 6, 2004 - link"1066 FSB might actually help more if it were paired with a 1 MB cache chip, but we'll have to wait a while to see that."
I think that's not the reason 1066FSB gives no performance increases in EE performance. I think it has to do with the fact that DDR2-533 has more than 33% higher latency than DDR-400 so in order to completely fill 1066FSB requirements you need higher than DDR2-533, preferrably DDR2-667. Do you see that DDR2-400 was slower than DDR2-533? Why is it slower when in dual-channel mode it perfectly matches 800MHz bus? Its because of latency. 800MHz bus needs DDR2-533 and 1066MHz bus needs DDR2-667.
JarredWalton - Saturday, November 6, 2004 - link#12 - The dedicated memory controller will become a separate chip from the Northbridge and Southbridge. We will end up with three chips. This decouples the RAM support from the NB, and since the NB has become quite complex, that makes it even easier for Intel to adopt a new type of RAM if it sees an advantage in doing so. I believe that it will also allow somewhat faster latencies, but only real product will actually let us know that for sure.
As far as the "independent" part and dual-channel vs. DIB (Dual Independent Buses), dual-channel is similar in that it's a wider, faster memory bus. I'm not sure whether the memory controller can actually send different requests out concurrently on each channel, however, and that is definitely something that DIB should provide. HyperTransport is a different approach to the same problem, but we'll see how "different" it really ends up being.
Right now, must of what we know about DIB comes from the Intel roadmaps, which are full of marketing information and short on technical detail. What we do know from the past is that with its deeper buffers and quad pumped FSB, NetBurst has always been more appreciative of memory bandwidth. 1066 FSB might actually help more if it were paired with a 1 MB cache chip, but we'll have to wait a while to see that. For dual-core (or multi-core) processors, however, it is definitely helpful for Intel. The same can be said of Xeons: DIB will give each socket much better RAM support, so Intel might see scaling similar to what Opteron is getting. I'm sure that's what they're hoping for, anyway.
sprockkets - Saturday, November 6, 2004 - linkAnd the best part is 1066FSB has no effect on performance whatsoever.
I'm not sure though what you mean by "dedicated memory controller." Don't all usual chipsets have a dedicated memory controller? And if you are saying too that Twin Castle has dual memory controllers, don't all current dual channel chipsets have 2 memory controllers already on it? Or does this mean that there will be 2 dual channel memory controllers on the NB? DOes this mean that each core then gets its own memory bank?
Even weirder, you say that there will be two buses per a socket, namely, for a dual core socket. Does that mean that each core gets a FSB? Wouldn't be more logical like AMD to have a 2ghz bus for both cores? Does this mean that Intel's 2 cores can't even talk to each other?
If you say so Intel...
Reflex - Friday, November 5, 2004 - link#9: You can prefer it all you want, but Intel has hit some fundamental laws of physics that won't go away. Expect larger cache's, higher FSB's, and multiple cores for the forseeable future...Which is good, it would be nice to see features rather than Mhz to increase performance in my opinion.
PorBleemo - Friday, November 5, 2004 - linkThis is basically giving Intel processors what the AMD processors had all along:
1. Independent Hypertransport Buses
2. 64-Bit Integer Processing
3. Real-Time Clock Throttling
We'll just have to see if the heat emissions will still be twice as high as the AMDs though. :)