Intel 65nm and Beyond (or Below): IDF Day 2 Coverageby Kristopher Kubicki on September 9, 2004 9:26 AM EST
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Next Generation Improvements
Of course, Montecito is already old news. 90nm is already old news. Strained silicon, low-k dialectrics and phase shifting lithography masks are also old news. Our interests belong to some of the technologies Intel discussed to bring the company out of the 90nm age in two years; into the 65nm interconnect era.
At AnandTech, we love roadmaps - particularly roadmaps with internal code names, wafer sizes and process technology. Stumbling into a development talk at the right time gave us a glimpse at Intel's 6 year plan for lithography.
Intel positioned itself to ramp a new lithography generation every two years - currently the 90nm D1D in Hillsboro, Oregon, houses the development technologies for 2005's introduction of 65nm technology. Some of Intel's most promising technologies fit into a nice line graph plotting process size against time.
Technologies like strained silicon and low-k dialectrics are just first steps for Intel. We are going to give a small primer on as much of these technologies as possible.