Intel Cheat Sheet

Intel IA32/EM64T Processors
CovingtonCelSlot 1266/3008K+8K7.535011866 
MendocinoCel ("A")Slot 1266-43316K+16K128K19250154661-2
MendocinoCel ("A")370233-53316K+16K128K19250154661-2
Coppermine-128Cel ("A")370533-76616K+16K128K28*18010666 
Coppermine-128Cel ("A")370800-110016K+16K128K28*180106100 
KlamathP IISlot 1233-33316K+16K512K7.5+37.2350203+L2661-2
DeschutesP IISlot 1266-33316K+16K512K7.5+37.2250118+L2661-2
DeschutesP IISlot 1350-45016K+16K512K7.5+37.2250118+L21001-2
DeschutesP II XeonSlot 2400-45016K+16K512K7.5+37.2250118+L21001-2
DeschutesP II XeonSlot 2400-45016K+16K1M7.5+74.4250118+L21001-2
DeschutesP II XeonSlot 245016K+16K2M7.5+148.8250118+L21001-2
KatmaiP IIISlot 1450-60016K+16K512K9.5+37.2250131+L21001-2
KatmaiP III BSlot 1533-60016K+16K512K9.5+37.2250131+L21331-2
TannerP III XeonSlot 2500, 55016K+16K512K9.5+37.2250128+L21001-8
TannerP III XeonSlot 2500, 55016K+16K1M9.5+74.4250128+L21001-8
TannerP III XeonSlot 2500, 55016K+16K2M9.5+148.8250128+L21001-8
Cascades**P III XeonSlot 2600-100016K+16K256K28.1180106-901331-2
CascadesP III XeonSlot 270016K+16K1M180210?1001-4
CascadesP III XeonSlot 2700, 90016K+16K2M1803851001-4
Coppermine**P IIISlot 1550-100016K+16K256K28.1180106-901001-2
Coppermine**P III BSlot 1533-100016K+16K256K28.1180106-901331-2
Coppermine**P III E370500-110016K+16K256K28.1180106-901001-2
Coppermine**P III EB370533-113316K+16K256K28.1180106-901331-2
TualatinCel ("A")3701000-140016K+16K256K28.113080100 
TualatinP III3701000-133316K+16K256K28.1130801331-2
TualatinP III S3701133-140016K+16K512K45.9130110?1331-2
WillametteP 44231300-200012Ku+8K256K42180217100 
WillametteP 44781500-240012Ku+8K256K42180217100 
FosterXeon DP6031400-200012Ku+8K256K421802171001-2
FosterXeon MP6031400, 150012Ku+8K256K512K42+37?1801001-4
FosterXeon MP603160012Ku+8K256K1M42+74?1801001-4
NorthwoodMob. Cel.4781400-280012Ku+8K256K130100 
Northwood**P 44781800-260012Ku+8K512K55130146-131100 
Northwood**P 4 "B"4782267-280012Ku+8K512K55130146-131133 
Northwood**P 4 HTT478306712Ku+8K512K55130146-131133 
Northwood**P 4 "C"4782400-340012Ku+8K512K55130146-131200 
Gallatin**P 4 EE4783200-340012Ku+8K512K2M55+123130231-237?200 
PrestoniaXeon DP6031600-300012Ku+8K512K551301001-2
PrestoniaXeon DP6042000-306712Ku+8K512K551301331-2
PrestoniaXeon DP6043067-320012Ku+8K512K1M55+611301331-2
GallatinXeon MP6031500-280012Ku+8K512K1M55+611301001-4
Gallatin**Xeon MP6032000-270012Ku+8K512K2M55+123130231-237?1001-4
GallatinXeon MP603300012Ku+8K512K4M55+246?1301001-4
Prescott 256?Cel D478/7752400-320012Ku+16K256K90133 
PrescottP 4 "A"4782400-280012Ku+16K1M12590112133 
PrescottP 4 "E"4782800-340012Ku+16K1M12590112200 
PrescottP 4 "E"T/7752800-???12Ku+16K1M12590112200 
PrescottP 4 "E"T/775???-???12Ku+16K2M90200/266 
BaniasCel M478M1300-150032K+32K512K130100 
BaniasP M478M900-180032K+32K1M130100 
DothanCel M478M900-150032K+32K1M90100/133 
DothanP M478M1000-240032K+32K2M90100/133 
JonahP M?65?2C

Intel IA64 Processors
DeerfieldItanium2PAC-6111000, 1500?16K+16K256K1.5M?130266?100512
* Die Size and/or transistor count is based off a larger CPU core with a portion of the die disabled.
** Various steppings/sources listed different die sizes.
*** The bus speed on the P4, PM, CM, and Itanium is quad-pumped, but the CPU multiplier is based off the listed speed.
**** Figures for Merced based off of 4M L3 cache version.
+ Figures for McKinley based off 3M L3 cache version.
++ Figures for Madison based off 6M L3 cache version.
+++ All Itaniums are said to be 512-way SMP capable, but this is more a factor of the motherboard and system design than the chip itself (I think).

Notes on the Intel side of things are similar to the AMD side. There are again a couple cores that have an asterisk, indicating that the core was a "downgraded" version of a faster core, mostly with the Celeron processors. The double-asterisks are for chips that had varying die sizes in the various steppings. This probably occurs to a small degree in most chips, but in the Cascades, Coppermine, and Northwood cores, the changes were well documented and rather drastic. Thoroughbred A to B in AMD was only a 4 mm2 die size increase, while Coppermine fluctuated between 106 mm2 to 90 mm2, and Northwood went from 146 mm2 to 131 mm2. My guess is that it was due in part to hand-optimizing the layouts of the cores, but if anyone has precise details on the hows and whys of the decreases, I would like to hear them.

In order to make the charts fit nicely within the space constraints, x86-64 was removed from the column lists. As of now, the only Intel CPUs that are known to include x86-64 support are the Nocona and Potomac cores. There will almost certainly be more in the future. The L1 cache of the P4 chips includes a trace cache, which stores decoded micro-ops, abbreviated uops. In the chart above, the trace cache corresponds to the L1 instruction cache found in typical CPUs, and 12Ku+16K means the cache has the ability to store 12,000 micro-ops as well as a standard 16KB of L1 data cache.

You can see that Intel also has 2C (dual core) designs in their roadmap, as well as a highly speculative 16C (sixteen core!) Itanium. Whether or not Tukwila will ever see the light of day is anyone's guess - it could simply be a mythical design that some hardware sites fantasize about. Transistor count on such a chips would likely be several BILLION transistors. (On a different note, I was recently up in Tukwila, WA purchasing a mountain bike from a pawn shop. They didn't have any processors for sale, unfortunately.)

In contrast to AMD, Intel has had several major architecture revisions during the past seven or so years. AMD pretty much stuck with the K7/Athlon core for all their processors, which was admittedly a very good design. Intel, with its deeper pockets, attacked on numerous fronts. First was the Pentium III line, which more or less ended in a draw with their rival AMD. Prompted by marketing - because "clockspeed sells" - Intel came up with a radical new architecture dubbed NetBurst, the basis of the Pentium 4. NetBurst was a success on the desktop, but it really was too power hungry for laptops, so Intel decided to pursue a completely separate architecture for its mobile processors, which is now also penetrating Blade and other low voltage markets. Finally, shortly after the launch of the Athlon 64, Intel countered with their reworked NetBurst architecture and the Prescott line of processors. Add to this the long-awaited launch of IA-64 (roughly ten years in the making!) which was a completely new architecture that was even more radical than NetBurst. Intel has been busy, needless to say.

For their desktop chips, SMP was available both officially and unnofficially. The Celeron chips were not intended for SMP use and were never validated (by Intel) to work in such configurations. However, enterprising motherboard makers like Abit with their BP6 board allowed users to run early Celerons in dual CPU configurations. Intel put a stop to that with Coppermine-128 and Tualatin-256 (if you can call it that) Celerons. The P3 Xeon chips were all "multi-processor" configurations, capable of up to 8-way SMP. Such support was more dependent on the motherboard and chipset, though, so most setups topped out at 4-way SMP. Intel had a chipset that linked two 4-way buses together for their 8-way configuration, while ServerWorks created a chipset and motherboard that supported 8-way directly. In theory, they could have even followed Intel's example and linked two buses together to have a 16-way SMP setup, although at that point motherboard size becomes a difficult issue.

Itanium and SMP is a special case that needs further clarification. SMP is not always listed in the above chart, but all Itaniums are said to be capable of 512-way SMP. This is really more of a factor of the motherboard(s) and system design than the chip itself. For example, special high-end clustered systems have been built using AMD Athlon MP and Opteron CPUs as well as Xeon chips that have as many as 128 chips in a "single" system. Itanium is a similar case with SMP. Motherboards with up to eight sockets exist for Itanium, but 512-way SMP requires special hardware beyond the motherboard. (Please feel free to correct me if that's wrong, but I'm pretty sure this is the case. I can't imagine what a motherboard for 512 Itaniums would even look like if it were to exist - 8x8 feet in size?)

Update: A couple people pointed out issues with the naming of the Celeron processors. At the time, Intel used "A" to designate processors that overlapped an existing model. So there were cacheless Celeron 266/300 processors, and the 266/300 with 128K L2 cache had an "A" suffix. This occurred again with the Celeron 533, and once more with the Celeron 1000/1100. In a similar vein, the Klamath core was only 350 nm, while Deschutes was 250 nm. It was initially listed as 350/250 as there were certain Deschutes cores that were released as a pseudo-Klamath, for instance the P2 300 MHz SL2W8. There was not any way to actually tell (other that word of mouth) which P2 chips had the Klamath core and which had the Deschutes core. The chart has now been corrected by putting in a 250 nm 266-333 Deschutes line.

AMD Processors Introduction to CPU Guides


View All Comments

  • Maverick Shiva - Thursday, November 25, 2004 - link

    The Articles are really beautiful.
    This was the complete description of the processors that are released and yet to be released.

    The technical details are really awsome and minute to the Detail.

    I would recommend that if you had Anand then you are really tech Savvy.
  • JarredWalton - Saturday, September 18, 2004 - link

    #72 - the article is now slightly outdated, being a whopping 20 days old. Sorry. We'll look at updating this with future articles, of course. Reply
  • Assimilator1 - Friday, September 17, 2004 - link

    An excellent article:)

    Though as someone mentioned the Semperon 2300 is missing ,this is clocked at 1.583GHz.
    Its listed in AMDs model 8 data sheets
  • endrebjorsvik - Wednesday, September 15, 2004 - link

    A very nice article with lost of good information!!

    Is there anybody who has all these datas collected into somethong like an exel-file or something.
  • jenand - Wednesday, September 08, 2004 - link

    JarredWalton: If you are going to update the roadmaps. Here is some good Itanium Info:
  • jenand - Wednesday, September 08, 2004 - link

    JarredWalton: If you are going to update the roadmaps. Here is some good Itanium Info:
  • romanl - Tuesday, September 07, 2004 - link

    Why is the Sempron 2300+ missing from a list of AMD CPUs? Reply
  • IntelUser2000 - Thursday, September 02, 2004 - link

    It was said that Willamette has 33% superior branch prediction due to its 4KB BTB buffer compared to Pentium III's(P3's had 512B).

    It was also said Pentium M's have 20% superior branch prediction to previous generation. Since we know that the major enhancements on branch prediction for Pentium M is enhanced indirect branch prediction and no BTB buffer increase, its likely its 20% over P3.

    Dothan does have superior branch prediction to 0.13 micron Pentium M, but it would probably be minor compared to Pentium 4's 33% superiority over P3.

    Taking P3 as baseline,
    -Pentium 4 adds 33% using 8x increase in BTB buffer, or 4KB compared to 512B
    -Banias takes P3 and puts enhancements to indirect branch predictor, which gives 20%
    -Prescott takes 33% from Willamette AND 20% from Banias
    -Dothan has Banias' 20% improvements plus something minor

    You say: " However, with the doubling of the cache size on Dothan, I can't imagine Intel would leave it with inferior branch prediction."

    Yeah but I can't imagine that Prescott will have inferior branch prediction than Dothan since its needed more on Prescott. And looking at per clock enhancements Dothan is not much faster than Banias, except Content Creation apps, telling again the enhancements are minor.

    Remember we are talking about how superior one branch predictor would be over another with same pipelines.

    I think of it this way: In terms of worst to best

    Pentium III
    P4 Willamette/Northwood/Dothan(I still think 33% improvement over P6 is greater than 20% in Banias+Dothan improvements)

    Oh yeah, there will be 4MB Fanwood parts but at 1.6GHz.

    Also since Itanium's core is half the size of Xeon and Intel also mentioned there will be twice the number of cores that Xeon has and Tukwila will be introduced ~2007 with quad-core Xeon then, Tukwila will have 8-core with Hyperthreading. Montecito is rumored to already have 600mm2 die size. Montecito has 24MB but Tukwila is rumored to have 32MB, not a lot increase, to possibly save space for more cores?

    I mean, Sun plans 32-core designs.

  • JarredWalton - Wednesday, September 01, 2004 - link

    Jenand, just an update, but it appears that Fanwood might not have 9M parts. The latest Intel roadmap talks about "Madison 9M/Fanwood/LV" parts in several places, but all the actual Fanwood parts are listed as 3M parts, and there's a not about pushing back the Fanwood 4M part.

    What is Fanwood? As of right now, I'm really not sure. Initially, I thought it was a renamed Madison, perhaps with more cache or for LV environments. Now, I'm starting to wonder if it might be a 90 nm version of Madison, or a version with more metal layers. Clock speeds are still in the Madison range, so that wouldn't really make sense, but why have the separate name if it's not somehow fundamentally different from Madison?

    And for what it's worth, the charts are now outdated somewhat with the announcement of the 6xx series of 2M L2 Pentium 4 parts. See latest Insider Stories.
  • jenand - Wednesday, September 01, 2004 - link

    Yes, Fanwood looks to be a 9MB L3 part. Strange. But i is limited to DP servers while Madison9M is for MP servers. just like Xeon MP end DP I guess.

    And no not many care about IA64 these days. Not strange. But with Millington I assume that will change! ;)

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