The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X, 1700X and 1700by Ian Cutress on March 2, 2017 9:00 AM EST
Thoughts and Comparisons
Throughout AMD's road to releasing details on Zen, we have had a chance to examine the information on the microarchitecture often earlier than we had expected to each point in the Zen design/launch cycle. Part of this is due to the fact that internally, AMD is very proud of their design, but some extra details (such as the extent of XFR, or the size of the micro-op cache), AMD has held close to its chest until the actual launch. With the data we have at hand, we can fill out a lot of information for a direct comparison chart to AMD’s last product and Intel’s current offerings.
|CPU uArch Comparison|
4M / 8T
4C / 8T
8C / 16T
|L0 ITLB Entry||8||-||-||-|
|L0 ITLB Assoc||?||-||-||-|
|L1 ITLB Entry||64||72||128||128|
|L1 ITLB Assoc||?||Full||8-way||4-way|
|L2 ITLB Entry||512||512||1536||1536|
|L2 ITLB Assoc||?||4-way||12-way||4-way|
|L1 DTLB Entry||64||32||64||64|
|L1 DTLB Assoc||?||Full||4-way||4-way|
|L2 DTLB Entry||1536||1024||-||-|
|L2 DTLB Assoc||?||8-way||-||-|
|Decode||4 uops/cycle||4 Mops/cycle||5 uops/cycle||4 uops/cycle|
|uOp Cache Size||2048||-||1536||1536|
|uOp Cache Assoc||?||-||8-way||8-way|
|uOp Queue Size||?||-||128||64|
|Dispatch / cycle||6 uops/cycle||4 Mops/cycle||6 uops/cycle||4 uops/cycle|
2x MMX 128-bit
Bulldozer uses AMD-coined macro-ops, or Mops, which are internal fixed length instructions and can account for 3 smaller ops. These AMD Mops are different to Intel's 'macro-ops', which are variable length and different to Intel's 'micro-ops', which are simpler and fixed-length.
Excavator has a number of improvements over Bulldozer, such as a larger L1-D cache and a 768-entry L1 BTB size, however we were never given a full run-down of the core in a similar fashion and no high-end desktop version of Excavator will be made.
This isn’t an exhaustive list of all features (thanks to CPU World, Real World Tech and WikiChip for filling in some blanks) by any means, and doesn’t paint the whole story. For example, on the power side of the equation, AMD is stating that it has the ability to clock gate parts of the core and CCX that are not required to save power, and the L3 runs on its own clock domain shared across the cores. Or the latency to run certain operations, which is critical for workflow if a MUL operation takes 3, 4 or 5 cycles to complete. We have been told that the FPU load is two cycles quicker, which is something. The latency in the caches is also going to feature heavily in performance, and all we are told at this point is that L2 and L3 are lower latency than previous designs.
A number of these features we’ve already seen on Intel x86 CPUs, such as move elimination to reduce power, or the micro-op cache. The micro-op cache is a piece of the puzzle we wanted to know more about from day one, especially the rate at which we get cache hits for a given workload. Also, the use of new instructions will adjust a number of workloads that rely on them. Some users will lament the lack of true single-instruction AVX-2 support, however I suspect AMD would argue that the die area cost might be excessive at this time. That’s not to say AMD won’t support it in the future – we were told quite clearly that there were a number of features originally listed internally for Zen which didn’t make it, either due to time constraints or a lack of transistors.
We are told that AMD has a clear internal roadmap for CPU microarchitecture design over the next few generations. As long as we don’t stay for so long on 14nm similar to what we did at 28/32nm, with IO updates over the coming years, a competitive clock-for-clock product (even to Broadwell) with good efficiency will be a welcome return.