Intel Pentium 4 3.0C – The First 800MHz FSB CPU

Feeding the Beast with more Bandwidth

The Pentium 4 architecture allows it to execute a maximum of 6 instructions per clock, courtesy of its multiple ALUs, FPUs and dedicated load/store units. However the number of instructions per clock (IPC) that are actually executed are nowhere near this maximum, thanks to a number of annoying factors. The fact of the matter is that most x86 code can't be made to be parallel enough on an instruction level in order to take advantage of a wide array of execution units, thus a number of the execution units of the Pentium 4 go unused during normal execution (this is where Hyper-Threading comes in handy).

Then there is the issue of actually getting instructions and data into the Pentium 4's pipeline so that they may occupy those execution units. Because of the extremely slow speed of memory (compared to the high speed on-chip cache of the CPU), the CPU burns a lot of execution time just waiting around to be fed new data to work on (or waiting for data that is necessary before existing operations may be completed).

Taking this idea of making the CPU wait to get data, you can see that if you decrease the amount of time that it takes the CPU to get data then the overall efficiency of the CPU will increase (its IPC will increase). Taking our highway/mall example from the previous page, let's focus on the number of sales that the mall can handle at any given point; assuming the number of sales are limited by the number of people we can get into the mall and the number we can get out of the mall after they're done, if we increase the speed of the two highways going to and leaving the mall then in theory, the number of sales transactions would increase. The number of sales that occur are analogous to the average IPC of a CPU, so you can see how increasing the FSB frequency and memory bandwidth would lend to a faster overall system thanks to an increase in IPC.

The benefit of a faster FSB (and higher bandwidth memory subsystem) will only become more and more clear as clock speeds increase; the faster the CPU gets, the more it will depend on getting more data, quicker in order for it to keep from becoming too bottlenecked. We won't see the full benefits of a 800MHz FSB and dual channel DDR400 until Prescott ramps up (90nm Pentium 4) in clock speed in 2004, but that isn't to say that performance won't improve today.