Core: It’s all in the Prefetch

In a simple CPU design, instructions are decoded in the core and data is fetched from the caches. In a perfect world, such as the Mill architecture, the data and instructions are ready to go in the lowest level cache at all times. This allows for the lowest latency and removes a potential bottleneck. Real life is not that rosy, and it all comes down to how the core can predict what data it needs and has enough time to drag it down to the lowest level of cache it can before it is needed. Ideally it needs to predict the correct data, and not interfere with memory sensitive programs. This is Prefetch.

The Core microarchitecture added multiple prefetchers in the design, as well as improving the prefetch algorithms, to something not seen before on a consumer core. For each core there are two data and one instruction prefetchers, plus another couple for the L2 cache. That’s a total of eight for a dual core CPU, with instructions not to interfere with ‘on-demand’ bandwidth from running software.

One other element to the prefetch is tag lookup for cache indexing. Data prefetchers do this, as well as running software, so in order to avoid a higher latency for the running program, the data prefetch uses the store port to do this. As a general rule (at least at the time), loads happen twice as often as stores, meaning that the store port is generally more ‘free’ to be used for tag lookup by the prefetchers. Stores aren’t critical for most performance metrics, unless the system can’t process stores quickly enough that it backs up the pipeline, but in most cases the rest of the core will be doing things regardless. The cache/memory sub-system is in control for committing the store through the caches, so as long as this happens eventually the process works out.

Core: More Cache Please

Without having access to a low latency data and instruction store, having a fast core is almost worthless. The most expensive SRAMs sit closest to the execution ports, but are also the smallest due to physical design limitations. As a result, we get a nested cache system where the data you need should be in the lowest level possible, and accesses to higher levels of cache are slightly further away. Any time spent waiting for data to complete a CPU instruction is time lost without an appropriate way of dealing with this, so large fast caches are ideal. The Core design, over the previous Netburst family but also over AMD’s K8 ‘Hammer’ microarchitecture, tried to swat a fly with a Buick.

Core gave a 4 MB Level 2 cache between two cores, with a 12-14 cycle access time. This allows each core to use more than 2MB of L2 if needed, something Presler did not allow. Each core also has a 3-cycle 32KB instruction + 32KB data cache, compared to the super small Netburst, and also supports 256 entries in the L1 data TLB, compared to 8. Both the L1 and L2 are accessible by a 256-bit interface, giving good bandwidth to the core.

Note that AMD’s K8 still has a few advantages over Core. The 2-way 64KB L1 caches on AMD’s K8 have a slightly better hit rate to the 8-way 32KB L1 caches on Core, with a similar latency. AMD’s K8 also used an on-die memory controller, lowering memory latency significantly, despite the faster FSB of Intel Core (relative to Netburst) giving a lower latency to Core. As stated in our microarchitecture overview at the time, Athlon 64 X2s memory advantage had gotten smaller, but a key element to the story is that these advantages were negated by other memory sub-system metrics, such as prefetching. Measured by ScienceMark, the Core microarchitecture’s L1 cache delivers 2x bandwidth, and the L2 cache is about 2.5x faster, than the Athlon one.

Ten Year Anniversary of Core 2 Duo and Conroe Core: Decoding, and Two Goes Into One
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  • Dobson123 - Wednesday, July 27, 2016 - link

    I'm getting old. Reply
  • 3ogdy - Wednesday, July 27, 2016 - link

    That's what I thought about when I read "TEN year anniversary". It certainly doesn't feel like it was yesterday...but it certainly feels as old as "last month" is in my mind and that's mostly thanks to i7s, FXs, IPS, SSDs and some other things that proved to be more or less of a landmark in tech history. Reply
  • close - Thursday, July 28, 2016 - link

    I just realized I have an old HP desktop with a C2D E6400 that will turn 10 in a few months and it's still humming along nicely every day. It ran XP until this May when I switched it to Win10 (and a brand new SSD). The kind of performance it offers in day to day work even to this day amazes me and sometimes it even makes me wonder why people with very basic workloads would buy more expensive stuff than this. Reply
  • junky77 - Thursday, July 28, 2016 - link

    marketing, misinformation, lies and the need to feel secure and have something "better" Reply
  • Solandri - Friday, July 29, 2016 - link

    How do you think those of us old enough to remember the 6800 and 8088 feel? Reply
  • JimmiG - Sunday, July 31, 2016 - link

    Well my first computer had a 6510 running at 1 MHz.
    Funnily enough, I never owned a Core 2 CPU. I had an AM2+ motherboard and I went the route of the Athlon X2, Phenom and then Phenom II before finally switching to Intel with a Haswell i7.

    Core 2 really changed the CPU landscape. For the first time in several years, Intel firmly beat AMD in efficiency and raw performance, something AMD has still not recovered from.
    Reply
  • oynaz - Friday, August 19, 2016 - link

    We miss or C64s and Amigas Reply
  • ArtShapiro - Tuesday, August 23, 2016 - link

    What about those of us who encountered vacuum tube computers? Reply
  • AndrewJacksonZA - Wednesday, July 27, 2016 - link

    I'm still using my E6750... :-) Reply
  • just4U - Thursday, July 28, 2016 - link

    I just retired my dads E6750. It was actually still trucking along in a Asus Nvidia board that I had figured would be dodgy because the huge aluminum heatsink on the chipset was just nasty.. Made the whole system a heatscore. Damned if that thing didn't last right into 2016. Surprised the hell out of me. Reply

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