MIPS Strikes Back: 64-bit Warrior I6400 Arrives
by Stephen Barrett on September 2, 2014 10:00 AM ESTFinal Words
When it comes to processors, enthusiasts and laymen alike can identify the three largest players: Intel, AMD and ARM. Those names are also not mutually exclusive: AMD utilizes ARM designs for consumer security coprocessors and in its Opteron A1100 server processor. There are other processors out there (e.g. IBM's POWER CPUs), but they're generally not as well known. That's also the case with MIPS.
Not everyone knows the name MIPS, but Imagination hopes to change that by offering a viable alternative to the embedded market dominated by ARM. MIPS already has a large presence in networking and embedded devices. Introducing the I6400 keeps MIPS relevant and places additional pressure on ARM. According to the provided numbers (admittedly from MIPS) and feature descriptions, the I6400 appears to compete with and even surpass the highly anticipated ARM Cortex-A53. Imagination projects general availability of the I6400 to SoC designers by December 2014. We can estimate end-user availability at least 6 to 9 months after that.
Consumers will most likely directly experience the MIPS I6400 CPU in low cost Android tablets and handsets. Due to Android's Java heritage, some applications will work out-of-the-box. Other applications using the Android Native Development Kit (NDK) targeting Intel or ARM ISAs will unfortunately be incompatible. Until MIPS achieves enough volume to convince application developers to code to the MIPS3264 ISA or stick with Java, MIPS Android devices will be second class citizens. This is something to keep in mind if you're purchasing a phone for yourself or a tech savvy friend. Of course, basic operating system features like email, phone, text, web browsing, and chatting should all work fine.
Intel has enjoyed dominance of its performance leading processors in non-handset settings for the better part of a decade. ARMs embedded low power heritage has emerged as Intel’s biggest threat as mobile devices have exploded and now dominate the computing landscape. As Intel and ARM continue to battle for the high end embedded market, Imagination and MIPS hope to erode away ARM’s mid-range and low-end core competency. As a consumer, we can lean back and enjoy the competition that will force each company to work harder each and every year.
The I6400’s revised MIPS3264 Release 6 ISA, instruction bonding, and SMT execution pipeline bring a refreshing set of new innovations to the small-core market. In our A53 coverage we noted ARM was pushing in-order CPU performance about as far as it could possibly go. I’m always happy to see we might have been wrong.
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Exophase - Wednesday, September 3, 2014 - link
Hi Alex, could you clarify what you mean by this comment? Superscalar and in-order are completely orthogonal properties, and I would expect that it always behaves like an in-order design regardless of SMT. Do you mean that in SMT mode it can only dispatch one instruction per cycle from the same thread? If that's the case, surely this is something that can be dynamically configured based on active thread count and not a fixed property of the processor?MartinT - Thursday, September 4, 2014 - link
I guess it is true strictly speaking that because of the two execution queues, it's limited to either super-scalar (single-threaded) or (scalar) multi-threaded operation at any one instant.I agree that it should read 'scalar' rather than 'in-order'.
mthrondson - Sunday, September 7, 2014 - link
To clarify - the I6400 can run superscalar on a single thread, or issue from two threads simultaneously. And it can switch which thread(s) it is working from on a per cycle basis.Guspaz - Tuesday, September 2, 2014 - link
They taught us MIPS32 assembly in school. My impression was that it was enormously simpler to write by hand than x86 assembly, much less of a headache to work with. Of course, assembly is almost entirely irrelevant these days.patrickjchase - Tuesday, September 2, 2014 - link
The main reason everybody learns MIPS (a.k.a. "DLX") in school is because the dominant architecture text was co-written by MIPS' inventor.Guspaz - Tuesday, September 2, 2014 - link
That's entirely possible. To be honest, I don't remember which textbook we used for our processor architecture course. But it was a breath of fresh air compared to x86 or even SIC. Having all the registers be general-purpose and letting you specify which register to put results into in the instruction was much easier to work with when writing assembly by hand on paper than x86, where every register seemed to be special-purpose, with different instructions putting results in different abstractly named registers.Exophase - Wednesday, September 3, 2014 - link
I've written x86 and MIPS assembly in real world applications, and personally I find both to be pretty annoying. When writing MIPS assembly, the poor addressing modes, delay slots, and range of immediates make it more cumbersome than x86. When writing x86 assembly, the lack of registers and three-address operands make it more cumbersome than MIPS. I haven't written much in x86-64, which I suspect is less annoying.dwforbes - Tuesday, September 2, 2014 - link
It's worth noting that for Android developers using the NDK, coding for MIPS, ARM64, or x86-64, is in the vast majority of cases nothing more than a compiler flag. There is seldom extra work necessary unless you've specifically used inline assembly.Samastrike - Tuesday, September 2, 2014 - link
I couldn't help noticing that the android logo used in the slide on the second page is holding a lollipop. Is this some confirmation of the official name when android L releases?Stephen Barrett - Tuesday, September 2, 2014 - link
I had the same thought. Wondered if someone would notice that. I'll let everyone conjecture on that topic :)