Two weeks ago Marvell announced their first PCIe SSD controller with NVMe support, named as 88SS1093. It supports PCIe 3.0 x4 interface with up to 4GB/s of bandwidth between the controller and the host, although Marvell has yet to announce any actual performance specs. While PCIe 3.0 x4 is in theory capable of delivering 4GB/s, in our experience the efficiency of PCIe has been about 80%, so in reality I would expect peak sequential performance of around 3GB/s. No word on the channel count of the controller, but if history provides any guidance the 88SS1093 should feature eight NAND channels similar to its SATA siblings. Silicon wise the controller is built on a 28nm CMOS process and features three CPU cores.

The 88SS1093 has support for 15nm MLC and TLC and 3D NAND, although I fully expect it to be compatible with Micron's and SK Hynix' 16nm NAND as well (i.e. 15nm TLC is just the smallest it can go). TLC support is enabled by the use of LDPC error-correction, which is part of Marvell's third generation NANDEdge technology. Capacities of up to 2TB are supported and the controller fits in both 2.5" and M.2 designs thanks to its small package size and thermal optimization (or should I say throttling). 

The 88SS1093 is currently sampling to Marvell's key customers and product availability is in 2015. Given how well Intel's SSD DC P3700 fared in our tests, I am excited to see more NVMe designs popping up. Marvell has known to be the go-to controller source for many of the major SSD manufacturers (SanDisk and Micron/Crucial to name a couple), so the 88SS1093 will play an important part in bringing NVMe to the client market.



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  • leminlyme - Tuesday, September 2, 2014 - link

    I mean but, haswell-e has 28 and 40 lanes? Forgive me if I'm mistaken, I don't understand all of this yet I'm just reading and learning now as a "new enthusiast" Reply
  • npz - Friday, August 22, 2014 - link

    You may be right. My own experience was from programming on AMD chipsets from several years ago where the PCIE root complex was (and still is) in the mobo chipset. Reply
  • npz - Thursday, August 21, 2014 - link

    Also Kristian, don't forget 8b/10b encoding. IMO the "theoretical max" figures quoted should never be the giga-transfers of the physical layer, but rather the post-8b/10b bandwidth of the data link layer since the theoretical max for data transmission will always be reduced by 20% Reply
  • Kristian Vättö - Friday, August 22, 2014 - link

    As repoman27 stated below, the 80% efficiency is after the 8b/10b encoding overhead, so I had that included already :) Reply
  • eSyr - Friday, August 22, 2014 - link

    PCIe Gen3 uses 128b/130b encoding. Reply
  • Stan11003 - Thursday, August 21, 2014 - link

    From Wikipedia:
    PCIe 1.x uses an 8b/10b encoding scheme that results in a 20 percent ((10−8)/10) overhead on the raw bit rate. It uses a 2.5 GHz clock rate, therefore delivering an effective 250 000 000 bytes per second (250 MB/s) maximum data rate.

    This scheme was used for PCIe 2.x also lucky for all of us PCIe 3.0 has a new scheme.

    PCI Express 3.0 upgrades the encoding scheme to 128b/130b from the previous 8b/10b encoding, reducing the overhead to approximately 1.54% ((130–128)/130), as opposed to the 20% overhead of PCI Express 2.0. This is achieved by a technique called "scrambling" that applies a known binary polynomial to a data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by running it through a feedback topology using the inverse polynomial. PCI Express 3.0's 8 GT/s bit rate effectively delivers 985 MB/s per lane, practically doubling the lane bandwidth relative to PCI Express 2.0.[21]
  • repoman27 - Thursday, August 21, 2014 - link

    The 80% number Kristian referred to is on top of the loss due to encoding efficiency. But yes, PCIe 2.0 is really 4 Gbit/s per lane because of 8b/10b encoding, yet PCIe 3.0 is still 7.877 Gbit/s (close to the nominal 8 Gbit/s) because of the switch to 128b/130b. Reply
  • DIYEyal - Thursday, August 21, 2014 - link

    Finally, the NVMe revolution begins.. (I'm aware it's not the first product, but it's good to see more NVMe controllers), although this seems like it's targeted more towards M.2 SSDs rather than desktop PCIe cards.. Reply
  • frenchy_2001 - Friday, August 22, 2014 - link

    There is absolutely no difference from a controller perspective between the form factors: both use PCIe interface and will deliver data over the NVMe protocol. M.2 is limited to 4x lanes at up to Gen3 while a PCIe card could use up to 16x lanes Gen3. As this controller is limited to x4 anyway, no restriction... (as a comparison, Intel SF3700 uses a Gen3 x4 controller too and is sold in PCIe card format only so far). Reply
  • MrSpadge - Thursday, August 21, 2014 - link

    This could be a nice competitor to SF3700. And I'd love to see a MX100-style drive based on this :) Reply

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