Interconnects

Finally, it’s time to talk about what lies ahead. One thing we haven’t talked about yet are the pressing issues of the near future. For example, there are major issues looming with interconnect delay that haven’t been solved yet. As we discussed in BEOL processing, the current system of wiring these metal layers uses copper with a dielectric in between the wires with a tantalum/tantalum nitride cap to support the next layer. However, the smaller the wires get, the worse electron mobility becomes.

This is roughly analogous to the issues that we see in the front end of line, which saw decreasing drive current for the same reasons. Combined with the capacitance produced between wires, there is dramatically increasing RC time delay in the connections made between transistors that hurts performance due to lower peak clock speeds. Ultimately, progress can only be made on this end by using lower k dielectrics and lower resistance materials to drive down both resistance and unwanted capacitance in these circuits.

Next Generation Lithography

There’s still more to talk about though. While we’ve managed to stretch 193mm immersion lithography further than anyone ever imagined, 10 nanometers is likely to be the end of the road for 193nm. Here, the future is unclear. Realistically, it seems that there are only a few techniques that will be viable at the next level. These include extreme ultraviolet lithography (EUVL), nanoimprint lithography, and electron beam lithography. Let's go over each one to try and understand what challenges are coming and which option may be the best in the long run.

EUV

On the surface, EUV is a relatively straight progression of the current 193i deep-UV (DUV) technology and should deliver the significant jump needed to advance lithography beyond 10 nanometer feature sizes. While this seems easy enough, there are a large number of issues that crop up from such a short wavelength (~13nm) of light.

First, the EUV light source itself is no longer a laser in most cases. This means that the energy efficiency of the light source is extremely low compared to current 193nm excimer lasers, and as a result an enormous amount of energy has to be used to generate an incoherent light source that is then filtered to only produce EUV.

Second, EUV is strongly absorbed by almost all matter. This means that the lithography must take place in a vacuum, which rules out techniques such as immersion lithography to further resolution enhancements. By using a strong vacuum for lithography, the amount of wafers that can be processed per hour drops dramatically as vacuuum chucks can no longer be used to hold the wafer, and the electrostatic chucks used must be heated to a stable temperature with a sacrificial wafer. Also, keeping the wafer heating from the EUV exposure becomes a significant issue because the immersion fluid that once cooled the wafer cannot be used.

In addition, it's impossible to use transmissive lenses because of this same issue. As a result, mirrors must be used to focus and reflect the EUV light on to the target. There are potential issues with EUV damaging the mirrors in the optical system, and in order to reflect the EUV light all of the mirrors and the photomask have to be coated with multiple layers that use interference effects to maximize reflected light. This also means that even minor defects in a photomask can result in an unusable photomask, as seen in the photo below.

Buried Defect on EUV Mask Blank / Guiding light / CC BY SA

Unfortunately, these defects cannot be seen using an electron microscope. In order to see these defects, an EUV microscope must be used. Outside of these challenges, EUV itself intrinsically has multiple issues that reduce resolution in some unexpected ways. First, shot noise becomes a serious issue. What this means is that it's fundamentally impossible to completely control the number of photons that are released into the photoresist. This means that the lines drawn by an EUV can be unacceptably rough unless enough photons are used to ensure that shot noise is statistically insignificant, but this only increases the power requirements for EUV lithography. To make things worse, by increasing the amount of exposure to the photoresist the material can be damaged by the sheer intensity of the heating effect of EUV.

Finally, because EUV is so energetic, it is a form of ionizing radiation. This means that when EUV light is absorbed by a molecule, electrons can be liberated. Unfortunately, this adds yet another source of uncertainty and also decreases resolution because the generated photoelectrons move randomly through the photoresist. In effect, all of these issues reduce the true resolution of EUV to somewhere around the 15-19nm feature size for a single exposure. In order to even get to 10nm and below, double patterning is required to reach the resolution necessary.

In short, the resolution gain from current 193nm technology is relatively small compared with the enormous expense and new design challenges. Based on how many delays have occurred with the introduction of EUV lithography, it may mean that a radically new system is needed to fabricate even smaller ICs. That's where nanoimprint and e-beam lithography come in.

Nanoimprint Lithography

Nano Imprint / UMD

This type of lithography is incredibly simple. This method is simply using a thermoplastic polymer coated onto the substrate (such as a silicon wafer), and then a mold is pressed down on the wafer to print a pattern. Once this is done, a pattern transfer technique such as plasma etching is used to etch away the resist as necessary to expose the pattern on the wafer.

While this technique is simple and can easily be used as a next generation lithography tool, there are also a number of flaws involved with this process. If the imprinting isn't done in a vacuum, there is a high likelihood that the mold will have air bubbles that alter the pattern in unpredictable ways. In addition, the template is susceptible to wear and tear, which means that resolution is lost as the mold is repeatedly used in imprinting. The imprint mold must also take into account uneven depth of imprinting based on the density of the pattern used and potential stretching of the resist. Finally, making the template itself requires extremely precise lithography, which means that it's limited by current generation lithography techniques in resolution. This isn't a solution by itself, which means it can only be used in conjunction with other methods.

Electron Beam Lithography

Electron Beam Lithography / SEMI

Just as we saw in the progression of microscopes, the early days were mostly focused on improving light microscopy with higher NA lenses and oil immersion, but today some of the highest resolution microscopes use electrons instead of photons. Similarly, electron beam lithography can generate some of the highest resolutions possible out of all the lithography techniques we've discussed in this article. This means that sub-10nm resolution is easily achieved. In fact, it's fully possible to do away with the resist and simply write the pattern directly on the silicon wafer, eliminating the resist as a potential bottleneck for resolution.

Unfortunately, this system is extremely slow. Rather than the 100+ wafers per hour of current photolithography techniques, electron beam lithography is often limited to less than ten wafers per hour. Using a single electron beam to write an entire 300mm wafer would take around 22 years. While thousands of beams can be simultaneously writing to the wafer to speed up the process, the electrons begin to affect the trajectory of other electrons in other beams. This requires complex modeling to compensate for such effects.

As with EUV lithography, shot noise becomes a significant issue despite a much easier ability to control the dose. This is because even small variations in the number of electrons can significantly effect the roughness of the lines drawn by the electron beam. There is also a strong need to choose a balanced energy for the electron, as excessively energetic electrons can cause significant secondary electron generation, but too little energy means the electrons are easily scattered. Both reduce resolution and can result in unacceptable defects for smaller process nodes.

Improving Transistor Performance: SOI to FinFET The Future: Improving Transistor Performance and Final Words
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  • DanNeely - Friday, October 10, 2014 - link

    A lot of them can only make n-type or p-type transistors. While that's not a problem for power or RF transistors; to control energy consumption and heat production you need both types to do CMOS logic gates.
  • JoshHo - Friday, October 10, 2014 - link

    While GaAs is popular in MMIC applications, it normally isn't possible to implement CMOS logic with such transistors.
  • Lux88 - Friday, October 10, 2014 - link

    Thank you very much for the much needed and very well written and illustrated introduction!

    How long does it take in real life to make a wafer with chips (with or without the testing)? Does it take hours, days or weeks to get a finished wafer with chips from silicon crystal?

    At the end you mention a rate of "100+ wafers per hour", but I understand it as "number of wafers we are working on in parallel" rather than "number of wafers from start to finish".
  • aicjofs - Friday, October 10, 2014 - link

    Time depends on the device and fab. Weeks though. I'd guess the average for any given chip(fron latest greatest down to simple microcontrollers) 3-6 weeks in the fab, another couple for testing packaging.

    He was talking about replacing a single photo tool(scanner/stepper) that does 100 wafers per hour with ebeam. There can be 10-100 scanners in fab, and as you say working in parallel.
  • ABR - Friday, October 10, 2014 - link

    Great article. Our society has poured vast resources into this area at multiple levels and achieved incredible results. I can't help but think that if we had been motivated to put this kind of engineering effort towards space projects we would not only be colonizing Mars by now, but mining asteroids and running orbital solar panels. Maybe we'll eventually come back to these things, with new powers bestowed by this "inner space" technology. Or maybe not.
  • pepone1234 - Friday, October 10, 2014 - link

    This article is amazing!! Thank you for writing this :D
  • Khenglish - Friday, October 10, 2014 - link

    You missed the biggest reason why SOI has gone out of fashion from microprocessors. Costs and fabrication are not a big deal. All you do is implant O2 deep into the wafer, then heat it to turn the implanted O2 into SiO2. This is 2 extra steps of 400 or so done when processing a wafer. No big deal.

    The problem is that there is no more transistor body connection to ground. This means that the body can build up charge like in flash memory. What it ends up doing is skewing the threshold voltage. When doing high voltage work with radio or power electronics with big transistors this is no big deal, but with microprocessors it is a significant. Even worse is this charge depends on the previous state of the transistor and how long it has been in that state, which is difficult to predict, and thus we have unpredictable performance swings with SOI.
  • JoshHo - Friday, October 10, 2014 - link

    This is a PD-SOI issue that falls under history effects mentioned in the article. FD-SOI doesn't have history effects as the body doesn't inherently have mobile charge carriers, which must be generated by band-bending.
  • Khenglish - Friday, October 10, 2014 - link

    So if FD-SOI gets rid of body effects then why is SOI not common? I supposed you can't just implant O2 and anneal for FD-SOI? Is sanding the wafer and growing SiO2 what needs to be done?

    The article also mentions temperatures, but the heatsink is attached to the interconnect side of the CPU instead of the bulk side from my understanding so this should have no impact.
  • JoshHo - Saturday, October 11, 2014 - link

    The biggest issue continues to be cost. While continuing to push bulk CMOS is more expensive in up-front cost, SOI has much higher fluid costs. There's also only one supplier of SOI wafers to my knowledge. (Soitec)

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