I must confess that until recently, I wasn’t well-versed in semiconductor physics or technology. While it’s rather easy to understand what a transistor does and some of the terminology thrown around, going deeper was tough. A great deal of the information on the internet is simply too cryptic to understand, even for those that want to learn. Seeing as how this site is all about the results of semiconductor physics and technology, this was the best place to share the knowledge that I've acquired.

Bandgap In Semiconductor / Pieter Kuiper

The simplest place to start is the materials. Silicon is incredibly important as a material in the industry because it’s a semiconductor. Of course, the name is self-explanatory, but there’s more to it. The key here is the band structure. Band structure refers to the “bands” of energy levels that form due to the sheer number of orbital states that can be occupied in molecules. Those that understand how electron orbitals work will point out that each energy level is discrete, but due to the sheer number of orbital configurations, a seemingly continuous distribution of energy can be seen. However, relatively large gaps still exist; known as a band gap, these are an energy state that an electron cannot occupy.

Band Filtering Diagram / Nanite

The question now is why this matters. The reason why it does matter is because of the Fermi level, or EF in the photo above. The Fermi level refers to the total chemical potential energy for a system of electrons at absolute zero. If the band lies above the Fermi level, electrons in the band can be delocalized from the atom, which means that it can carry current. This band is called a conduction band. If the band is below the Fermi level, this means that the electron is bound to an atom. This band would be a valence band.

Intrinsically, a semiconductor should have its Fermi level at the midpoint of the band gap. This is true of both insulators and intrinsic semiconductors, but a semiconductor’s band gap is extremely small. In fact, it’s small enough that electrons can jump the band gap as seen in the photo above because of thermal energy that will always exist in real world situations. While this property alone isn't particularly useful for digital logic, doping a semiconductor can have significant effects on the band structure. This means that the distribution of electrons in the valence band or conduction band will change.

This is where I have to introduce even more terminology. Depending on how the distribution is changed, a semiconductor is dubbed either a p-type or n-type semiconductor. If the band structure is such that free electrons are more easily generated, it becomes an n-type semiconductor. If the structure is such that electron “holes” are generated, it becomes a p-type semiconductor. In this case, electron holes refers to a place where an electron could exist, but doesn’t. Such a hole still conducts current. Look carefully at the p-type diagram once again. Because the valence band is so close to the Fermi level, electrons tend to stay in the valence band at lower orbitals. This is means that there are "holes" where an electron could be, which makes it a charge carrier. It's also worth noting that the diagram above isn't totally accurate, as doping normally introduces more bands instead of shifting their positions, but the concept is the same.

PN Junction Equilibrium / TheNoise / CC BY SA

What really makes things interesting is when a p-type and n-type semiconductor are placed next to each other. Because p-type semiconductors tend to have electron holes and n-type semiconductors tend to have an excess of electrons, there will be a diffusion of holes and electrons to try and equalize charge at the junction. Because of this diffusion process, the area around the junction becomes charged positively at the n-doped region and negatively at the p-doped region. This happens because the n-doped region is losing electrons, making the area positive while the p-doped region is losing holes, therefore becoming negative. The result is that an electric field is generated which opposes this diffusion and eventually reaches equilibrium. The area where this process occurs is called the depletion layer, as these ionized areas are stripped of charge carriers and therefore unable to carry current with the band structure that already exists.

PN Band / Saumitra R Mehrotra & Gerhard Klimeck / CC BY

This p-n junction is incredibly important in solid state electronics. In fact, the system we just described can be used as a diode, which is a device that only allows current to flow in a single direction. If a battery is connected with the positive terminal at the p-type semiconductor and the negative on the n-type semiconductor, the holes in the p-type and the electrons in n-type are all pushed towards the junction, which causes the depletion zone to shrink. This means that the electric field repelling the current decreases, and current is allowed to flow across the junction.

Transistors and CMOS Logic
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  • dragonsqrrl - Thursday, October 9, 2014 - link

    Article like non other, thanks. Reply
  • tarlinian - Thursday, October 9, 2014 - link

    The description of the wafer processing is pretty much completely wrong. FEOL line processing involves almost no direct oxide etches. It also completely skips shallow trench isolation and all the CMP steps involved in patterning. The wiring of the chip has no metal etch anymore either. Every metal layer in a modern (<10 years old) logic chip is produced via damascene patterning of copper. (You etch a dielectric, fill the trenches with copper and then polish the copper back.) Reply
  • JoshHo - Thursday, October 9, 2014 - link

    Much of the article is definitely quite simplified but the intent is to give a general idea of the process. I'd love to learn about this subject in more depth though. Reply
  • revoltracers - Thursday, October 9, 2014 - link

    I am printing this one out. Reply
  • tuxRoller - Thursday, October 9, 2014 - link

    Could you expand on "the holes in the p-type and the electrons in n-type are all pushed towards the junction, which causes the depletion zone to shrink" a bit?
    Connecting the + terminal @ the p semiconductor means you'll get electrons flowing into the n semiconductor. This should result in the n semiconductor being even more relatively negative, and the opposite on the p semiconductor.
    If that's the case, why wouldn't that cause a larger delta V at the junction?
    Reply
  • JoshHo - Friday, October 10, 2014 - link

    The issue here is that there is a diffusion of charge carriers. The negative end provides the potential that pushes electrons towards the depletion layer on the n-side, which has holes due to the diffusion that was previously discussed. The positive end pushes holes towards the center on the p-side, which has electrons in the depletion region. Reply
  • tuxRoller - Friday, October 10, 2014 - link

    Damn.
    IOW, I got my field directions mixed.
    Thanks.
    Reply
  • dyc4ha - Thursday, October 9, 2014 - link

    Thanks! I am still trying to digest this article, but nevertheless I know I am enjoying it! Keep it going Reply
  • PacificToast - Thursday, October 9, 2014 - link

    Nice piece. It's great to see easily accessible high-level articles being written on micro-nano IC tech. I work for a large foundry, and its often hard to explain to people what's happening inside their devices. Reply
  • Dr.Neale - Friday, October 10, 2014 - link

    First, a minor typo appears in the High-k / Metal Gate section, 3rd paragraph, 1st sentence: "comlexity" should be "complexity". (Amazing that in an article of this complexity I could only find one typo!)

    Second, I noticed that there was no mention of compound semiconductors like GaAs. I was under the impression that while many technical issues have been resolved, it remains prohibitively more expensive than silicon. Is this indeed the case, or are other factors more of an issue than cost?

    Great article, by the way, especially in regard to FinFET transistors. Makes things much clearer in my mind.

    Thanks, Josh.
    Reply

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