The interAptiv family brings multithreading to the table, something which ARM hasn't started implementing yet. As our Lava Xolo smartphone revealed, implementing simultaneous multi-threading is highly beneficial for performance, particularly in current day workloads.

MIPS claims that 3 interAptiv cores deliver performance similar to / slightly exceeding what could be obtained from 2x Cortex-A9 / 3x Cortex-A5 cores with the same silicon area. Of course, CoreMark numbers heavily favor the interAptiv cores.

In the interAptiv family, the CPU execution pipeline is shared by multiple threads, which allows the mitigation of the performance impact of memory access latencies. Since interAptiv is targeted towards real time workloads, a hardware scheduler enables a better QoS.

MIPS terms the threads as VPEs (virtual processing elements). The pipeline itself is 9 stages long and is in-order. An optional multi-threaded IEEE 754 FPU can be added if necessary. DSP ASE is available, as is EVA (similar to the proAptiv family). The CPS used with the multi-core interAptiv family has the same features as that used by the proAptiv.

Compared to the proAptiv, the interAptiv core architecture allows for core clock shutdown during outstanding bus requests, intelligent way selection in the L1 instruction cache and 32-bit L1 data cache access as options for power reduction. [ Update: Intelligent way selection in the L1 instruction cache is also available in the proAptiv family ]

In the TSMC 40nm G process, the interAptiv family members can run at up to 1 GHz for applications involving multi-threading with QoS and at up to 1.2 GHz for multi-threading without QoS. If DSP ASE is not desired, implementations can run at up to 1.5 GHz for networking applications. [ Update: The quoted frequency numbers are 'sweet spots' in terms of power consumption and other application specific requirements. As mentioned in the previous section, the frequency of operation can be scaled depending on customer requirements and is not related to the presence of absence of DSP ASE / QoS ]

The microAptiv architecture is a superset of the M14K/c cores with microMIPS code compression support. With integrated DSP ASE, signal processing comes in at a lower cost. There are options to implement without caches / MMUs depending on the application.

This 5 stage pipeline architecture can run at up to 400 MHz in a 65nm LP process. MIPS also presented a side-by-side comparison of the Cortex-M4 and the microAptiv family:

Obviously, the extra features don't come without an area penalty. In a 90nm LP process, Cortex-M4 has a floorplanned area of 0.17 mm2 compared to the 0.42 mm2 of the microAptiv MCU (cacheless version). [ Update: MIPS claims that the area numbers are not apples-to-apples comparison. Under similar implementation conditions in 90LP - read, area optimized - MIPS expects the microAptiv family to have only 0.01 mm2 extra area. Our data is from ARM's Cortex-M4 specifications. We agree it is difficult to compare the area requirements, but readers should note that there is no free lunch when it comes to feature set vs. die area ]

proAptiv Architecture Miscellaneous Thoughts and Final Words


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  • Daniel Egger - Saturday, May 12, 2012 - link

    The problem is: Maybe MIPS just woke up but as a matter of fact this market is long gone for them since they don't have the force to push anything around. Intel is a much bigger company trying to achieve the very same thing but they're barely moving forward.

    Of course one is free to assembly SoCs with MIPS cores but why would one do that? Most of the auxiliary ICs needed for the completely picture are using ARM-optimized or ARM-only interfaces so there're almost no components to choose from while the generic ones (utilizing PCI(e) or USB) use far too much energy and/or space and are usually not synthesizable. Then there is the price issue: MIPS SoCs for mobile devices will be low volume at the beginning and thus quite expensive compared to ARM devices. And then there's the tooling and compatibility issue: The MIPS hardware support for e.g. Android is rather limited and alpha quality in most areas while ARM and even x86 are quite mature. And then there's the market compatibility issue: Good software needs natively compiled code to perform well, ARM is the default here and x86 will bring an ARM emulator to the table; MIPS can't do snitch here...

    My prediction: Maybe we will see some insane multi-chip prototypes or even one or two (likely Chinese) SoCs and systems based on that for absolute low end phones but they'll go nowhere in the market.

    I'll be far more interesting to see how long it'll take e.g. Ralink to pick up the Aptiv Series for their WLAN SoCs. ;)
  • Scipio Africanus - Thursday, May 10, 2012 - link

    For anyone who is old enough and fortunate enough to remember the SGI workstations, its pretty sad to see what's become of MIPS based machines. My college was an SGI shop and our 6-CPU R4400 SGI Octane server was an awesome sight to behold in the days of Pentium 1 and 2. So were the Indy and Indigo workstations where we would play GLQuake. Reply
  • martinw - Friday, May 11, 2012 - link

    Octane was a dual socket workstation, not a 6 socket server. Perhaps you are thinking of a Challenge server?

    I remember when the first R4k and the first R10k SGI machines came out - amazing performance at the time...
  • Scipio Africanus - Friday, May 11, 2012 - link

    You're right, it was a Challenge L server now that I think about it.

    During the introduction tour, we saw a real time rendering of a shark. Of course it looked cartoonish by any standard today but the fact that the motion was fluid and it was being rendered real time was jaw dropping. Seeing that and be awestruck is stuck in my memory permanently.
  • iwod - Thursday, May 10, 2012 - link

    1. I am pretty sure MIPS is older then ARM. While the article points to ARM being older.

    2. Do this news IPs have something similar to big.LITTLE?

    3. Performance / Mhz doesn't matter, Performance / Watts does.

    4. Apart from MIPS being used in Network equipment, and some set top box, and some Tablet. There are no new market that are using them. Network Market uses them solely because they dont want to reinvest in software and hardware. ( Hence why our Router is still dog slow ).

    And I also dont understand why Tablet Maker would want to use MIPS instead. How much cheaper is it?

    5. Even NAS moved to ARM based SoC ( Kirkwood ) instead of MIPS many years ago.

    6. Set Top Box maker are now moving to wards ARM solution since there are many more ready made solution.

    So yea, What exactly does MIPS have an advantage? Unlike Intel who could damn well push Atom into 14nm Node and just Brute Force winning by Manufacturing Technology.
  • jamyryals - Friday, May 11, 2012 - link

    Nice article Ganesh, I learned a lot. Keep up the good work. Reply
  • Avenkidur - Saturday, May 12, 2012 - link

    If process technology plateaus, or even slows, and we stop harvesting the benefits of shrinkage, power efficiency, speed, and cost -- could it be an opportunity for MIPS and Micro-Kernels? Technology is at the point where the best design is allocating all resources to the computer to think for itself instead of trying to guess ahead?

    They both seemed ahead of their time, elegant in theory but challenged to deliver on performance on an open playing field.

    ARM is doing well primarily because it is more power efficient than x86 and it crossed the threshold of good enough for smartphones. MIPS is fundamentally even more power efficient than ARM, and it will easier scale to more cores.

    I mentioned Micro-Kernels because I feel it is the same design philosophy, just in software. They've got an opportunity coming up to be a single OS that spans a broad range of targeted usages -- they can securely enable and disable drivers on the fly, and the core codebase is not polluted with legacy needs so the whole thing can be secure, while rapidly iterating into new possible features (it's not just sound and video now. Multiple microphones, NFC, motion sensing, computer vision --- who knows what else might be designed in at a deep level.)

    iOS is only 5 years old, and you feel it: on what the new devices can't do (fast-switching instead of multi-tasking, that animated lag coverup), on the old devices that can't keep up under the updates that have features bundled in they can't use, the need to restart to update the OS, a software crash can take the whole system down, the multitude of ways to hack into a strangers' phone, the extra work necessary just to port one application to AppleTV, iPod/iPhone, iPad, iMac.
  • Avenkidur - Saturday, May 12, 2012 - link

    duh.. I forgot to mention that Micro-Kernels are the best suited to take advantage of multiple cores, which is the first reason I brought them into a post about it maybe being a chance for MIPS to make a dent Reply
  • xenol - Saturday, May 12, 2012 - link

    It's nice to know that ARM isn't going to be the only 32-bit guy in the microcontroller universe once the 8-bit/16-bit guys start phasing out. I just hope others take MIPS in.

    I also guess that depends on whether or not software development tools for Aptiv are up to snuff.
  • ET - Monday, May 14, 2012 - link

    That's the best article about these processors that I found. I love it that you went to MIPS for clarifications. Reply

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