A Tale Of Two Thunderbolt Storage Devices: Seagate's GoFlex Desk and Western Digital's Thunderbolt Duo

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• bdipert - Monday, May 14, 2012 - link

  Thanks for the clarification, isulzer, very interesting!

• ssddaydream - Monday, May 14, 2012 - link

  One thing that would be incredibly useful is direct PC to PC connection with USB 3.0 networking.
  Anybody else down for 4.8 gbps transfers with a cheap $15 cable?
  Apparently, all you need a USB 3.0 crossover cable and each computer motherboard with capable drivers.
  Anandtech, can you guys take a look at this? Some things in this industry just boggle me, such as a lack of an obvious USB 3.0 networking solution...
  Thanks!

• peterfares - Monday, May 14, 2012 - link

  WHY does Thunderbolt need to carry DisplayPort AND PCIe. Wouldn't it have been easier to add pins to a displayport receptacle or create a new port for the PCIe data? Why do we need these multiplexing chips in each device when we could have just used straight PCIe? Even better, integrate the PCIe lanes right into a USB receptacle. It's a data bus, should it not be in a data port?
  
  If you want one cable to a docking station/display, they could have easily mandated that one Thunderbolt port must be right next to a displayport port.

• repoman27 - Monday, May 14, 2012 - link

  Apple was already shipping Macs with mini-DP connectors that were capable of pushing 17.28 Gbps worth of packetized data over a single cable. It's only common sense to look at that and say, "Wait a minute, why just use this for display data? Why not make it full-duplex and use it for transporting PCIe packets as well?"
  
  Digital display interfaces are the only ports commonly found on PC's that are even in the ballpark of Thunderbolt from a bandwidth perspective, so the marriage of the two is actually fairly logical.
  
  Mini DisplayPort connectors already pack 20 pins in a 33 mm^2 cross section. That's pretty dense, there's not really room for adding more pins. Plus, by keeping the same physical connector as mini-DP, it's easier to maintain backwards compatibility with existing DisplayPort gear.
  
  Besides, adding more pins to the connector would mean adding more conductors to the cable, and Thunderbolt cables are already complex and expensive enough as is.

• Glindon - Monday, May 14, 2012 - link

  So you'd rather have two cables hanging out of your computer than one? That's a silly argument. Why not have three or five then?
  
  I don't get all the hate for thunderbolt. When intel first demoed it everyone was raving about how great it would be, but once it came on macs first everyone said how dumb and stupid it was. At least pcs are going to get it now so we can get more devices for it and then it can suddenly become "cool" again.

• aliasfox - Monday, May 14, 2012 - link

  Actually, if I remember correctly, Intel tried to get LightPeak (as it was called while under development) integrated into a next generation USB port, but the consortium told them to take a hike - patents/royalties and customer confusion being named as primary issues with that implementation. That's when Apple stepped in and offered their mDP design - Apple was one of the originators, but it's a royalty free design as far as I've heard - part of the reason why AMD uses it for Eyefinity. Intel develops the tech, Apple offers the plug design, and in turn, gets first dibs on it.
  
  Sony *did* implement a variant of TB/LightPeak on its Vaio Z (the one that has the external 6630m) that utilizes a USB port, but that's not standard.

• repoman27 - Monday, May 14, 2012 - link

  By "the consortium" I reckon you're referring to the USB-IF, which was actually formed by none other than Intel. I know that the USB-IF and Intel both frowned on Sony's non-standard implementation, despite the fact that it closely resembles a lot of the early demonstration hardware, but did Intel ever actually try to convince the group to sanction the adoption of a USB style connector for Light Peak?
  
  Also, DisplayPort is a royalty free specification maintained by VESA. Apple developed the mDP connector and agreed to license it for free, and VESA subsequently included it in the DP 1.2 specification. This all happened over a year prior to Thunderbolt arriving on the scene.
  
  I'm pretty sure Apple got first dibs on Thunderbolt because they agreed to buy 18 million additional chips from Intel in 2011 if they got an exclusive on it.

• Impulses - Monday, May 14, 2012 - link

  Nice review and flyby of the current Thunderbolt market... The overuse of parenthesis on the first couple of pages was odd tho (almost like some were added by an editor?).
  
  Anandtech seems pretty bullish on the virtues of Thunderbolt in general but outside of laptop/docking station scenarios I still see very little upside to it, and that prospect alone (plus the super high adoption cost) won't help propel the interface to wide adoption anytime soon.
  
  It's a shame too because some of the long term applications that have yet to materialize are very appealing, things like external GPUs, etc. If costs don't drop fast enough it's gonna be Firewire all over again, hopefully Intel stands behind it long enough for that not to happen.

• name99 - Monday, May 14, 2012 - link

  "Its 480 Mbps theoretical peak bandwidth,"
  
  Just like with WiFi, please for the love of god explain this stuff correctly. The issue is not that this is a "theoretical" or a "peak" bandwidth, it is that this is the PHY bandwidth, that is, it is the speed at which bits (all the bits) are dumped onto the wire (or into the air).
  So why doesn't that match the actual goodput (ie the throughput of my file bits)?
  
  The minor factor is that there is a variety of overhead that is required to correctly frame and describe each packet. There are bits that describe the purpose of the packet, its length, its source and destination, etc. In the case of WiFi (I don't know about USB2, but I expect these are necessary at the speeds of USB3) there are bits that allow the receiver to track how the signal is degraded as it travels and thereby compensate, and so on and so on.
  
  The major factor is that these are not point to point links, they are shared, which means that some sort of protocol (a MAC) is required to decide who gets to talk at any given time, and how to recover when a mistake is made and two parties talk at the same time. Unfortunately the general rule for MACs is usually that people seem far less interested in working hard to make them efficient than they are in working hard to make the PHY efficient. So what one sees is that an awful lot of time is wasted in MAC overhead.
  
  The historical pattern for WiFi has been that each release includes various new smarts that can allow the the MAC overhead to drop to about 25% (ie actual goodput under optimal conditions is around 75% of the PHY rate), but that the chip vendors actually implement only enough of these smarts (which are always labelled optional in the spec) to get this goodput to a little over 50%.
  
  The historical pattern for USB, which has stood still for so long, is that at first we had the same sort of situation --- crappy MAC implementations that gave us a real world throughput of about 50% --- but, with nothing else to do, the chip vendors ramped up their chips to use every smart possible in the MAC, given us the current goodput under optimal conditions of about 65%. Point is --- the correct way to describe this is that USB2 has a PHY rate of 480Mbps, and an maximum goodput (taking into account both overhead bits and the MAC) of around 320Mbps.
  
  The same is going to be just as true of something like Thunderbolt, when we get to the point of stressing it hard. There is a PHY rate, there are overhead bits for addressing, framing, packet description, training, etc; and there is some sort of MAC. I know nothing about the Thunderbolt MAC, and so have no opinion about whether it's an inspired or a crappy design (or the extent to which chips can make more or less efficient use of it). These would all be good topics for a future article.

• repoman27 - Monday, May 14, 2012 - link

  <blockquote>Granted, Thunderbolt's 8b/10b encoding scheme reduced the effective peak bandwidth to 8 Gbps...</blockquote>
  
  Thunderbolt provides a full 10 Gbps per channel to the upper layers—there's no 8b/10b in that figure. Anand achieved just over 8 Gbps of throughput with the Pegasus R6. Taking in to account other sources of PCIe overhead, such as packet framing and link maintenance, that number is about spot-on for a 10 Gbps link. Also, the PCIe data may be transported on more than one channel of a Thunderbolt cable, however the current controllers are limited to 10 Gbps of PCIe throughput because they only contain a single PCIe to Thunderbolt protocol adapter.
  
  <blockquote>...perhaps, alternatively, the HDD is getting a portion of its power allocation supplied directly over the Thunderbolt link from the connected computer system.</blockquote>
  
  I doubt either of these devices utilize bus power to a significant degree, because according to Apple, only the first device in a Thunderbolt chain can be bus powered.
  
  <blockquote>Such a feature allows the system-side Thunderbolt controller to "see" each Thunderbolt Duo as a single bus peripheral, thereby enabling WD to accurately claim that you can daisy-chain numerous drives to each other and the system before you violate Apple's six-max specifications.</blockquote>
  
  The 6 device limit only pertains to the number of Thunderbolt controllers that can be in a chain. You can hang as many PCIe attached devices as you like off of a single Thunderbolt controller. A good example of this is the Apple Thunderbolt Display—in System Information it shows up as many separate devices, but it still only counts as one Thunderbolt device.
  
  As far as Thunderbolt product pricing goes, I think we're just looking at a scary BOM cost, which will hopefully be alleviated some with the arrival of Cactus and Port Ridge controllers.
  
  And you can use the GoFlex desk adapter with any old drive, so I'm surprised you didn't give that a whirl.