Availability and Controller support

Just to make this clear, TLC isn't anything new. For example Hynix had a 32Gb 48nm TLC die in 2008. This is because TLC was originally used for devices like USB flash drives, where its poor endurance would be negligible. Most SSD OEMs have been toying with TLC SSDs for at least a year now but we haven't seen any commercial products. OCZ had originally planned to introduce its first TLC based SSD in the Q1 2012, however TLC pricing simply hasn't made sense yet. Unless OCZ can leverage a significant cost savings over 2-bit-per-cell MLC, the added headaches of bringing a lower performing TLC part to market don't make sense.

However there's still significant motivation to migrate towards TLC NAND. Further bringing down costs, particularly for consumer SSDs aimed at light, particularly read heavy workloads makes a lot of sense. Increasing pressure from Intel to deliver cheaper SSD enabled Ultrabooks, and Apple's desire to move all mainstream Macs to solid state storage are two major motivations. MLC NAND pricing will eventually get low enough to meet these (and more) needs, but TLC definitely accelerates the process.

TLC does require controller and firmware support. In the client SSD space only OCZ has been aggressive with announcing that its Indilinx Everest controller supports 3-bit-per-cell NAND. 

Adding controller support for an extra bit per cell is more than just updating the datasheet and claiming it works. The ECC engine needs to be updated as the controller will face more frequent and more severe errors with TLC NAND (and its associated lower endurance rating).

Maintaining low write amplification is even more important with TLC NAND. With significantly fewer available program/erase cycles, burning through them due to high write amplification isn't acceptible. While NAND endurance isn't really an issue for most client MLC drives, it may be an issue for TLC based drives. 

Weaknesses of TLC: One Step Worse than MLC Final Thoughts


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  • Kristian Vättö - Saturday, February 25, 2012 - link

    I just used the names that manufacturers use. If you look at e.g. Micron's part catalog (linked below), they use SLC, MLC and TLC. I agree that the naming is misleading because MLC should refer to any NAND with multiple bits per cell. TLC is sometimes called as 3-bit-per-cell MLC or just MLC-3 but the TLC name is gaining more momentum all the time.

  • foolsgambit11 - Sunday, February 26, 2012 - link

    Thanks. Reply
  • Taracta - Sunday, February 26, 2012 - link

    Shouldn't the TLC be 64Gb? It holds twice as much information as MLC as MLC hold twice as much as SLC. Each increment in bits doubles the information stored as stated in the article, SLC 2bits stored, MLC 4bits stored and TLC 8bits (1 BYTE) stored. Reply
  • Taracta - Sunday, February 26, 2012 - link

    You are dealing with base-2 values. Each additional bit doubles the amount of data that is stored. You even have the correct values in the begining of the article. SLC stores 2 bitsof information 0 and 1, MLC stores 4 bits of information 00, 01, 10, 11 and TLC store 8 bits (1 BYTE) of information 000, 001, 010, 011, 100, 101, 110, 111 yet further down in the article you are stating that TLC stores only a third more that of SLC. You are confusing the bit place holder with the actual information that is being stored. TLC has an additional bit place holder compared to MLC which has an additional bit place holder compared to SLC. Each bit place holder increases the storage capability by a power of two (2). Reply
  • Kristian Vättö - Sunday, February 26, 2012 - link

    SLC stores 1-bit per cell/transistor and the value can be either 0 or 1. It cannot be 0 and 1 at the same time.

    MLC stores 2-bits cell. This means the value can be either 00, 01, 10, or 11. However, it can only be programmed to have one value. One MLC cell cannot store e.g. 00 and 01 at the same time. One 0 or 1 is one bit of data, i.e. 00 is two bits of data. I don't know how you are coming up with four bits, maybe you are mixing it with the voltage states (each value needs its own voltage state so when you program a cell to e.g. 00, it will be read as 00).

    TLC just increases the bits per cell to three which means the possible values are 000, 001, 010, 100, 011, 110 101, and 111. Again, eight voltage states and three bits per cell.

    Each additional bit per cell increases the voltage states by a power of 2 (in math terms: 2^n, where n is the amount of bits per cell). Amount of bits per cell is just n, it's not a power of two. MLC is 2*1=2, and 2 is 100% bigger than 1. TLC is 3*1=3. and 3 is 200% bigger than 1 but only 50% more than 2.
  • Taracta - Sunday, February 26, 2012 - link

    Ok let me make it simple because I still think you are confusing yourself.

    SLC possible values are 0 or 1 which is equal to 2 values with is 2^1

    MLC possible values are 0, 1, 10 or 11 which is equal to 4 values which is 2^2

    TLC possible values are 0, 1, 10, 11, 100, 101, 110 or 111 which is equal to 8 values which is 2^3

    Therefore each TLC which stores 8 values (3bits) which is twice that of a MLC which stores 4 values (2bits) which is twice that of a SLC which stores 2 values (1bit)

    Is this right?
  • KitsuneKnight - Sunday, February 26, 2012 - link

    He's not confusing himself, you're confused about binary numbers and bits.

    "Therefore each TLC which stores 8 values (3bits) which is twice that of a MLC which stores 4 values (2bits) which is twice that of a SLC which stores 2 values (1bit)"

    Don't confuse the amount of bits of storage, with the maximum value it can hold.

    Since you seem to be getting confused with binary numbers, lets work with decimals numbers for a bit.

    Lets say an 'SLC' can represent the values 0-9. An MLC can represent the values 0-9, 0-9 or 00-99 (that's two sets of 0-9 next to each other!). A TLC can represent the values 0-9,0-9,0-9 or 000-999. It should be patently obvious that an TLC doesn't have 100 times the capcity of an SLC cell! A /single one/ can hold a VALUE 100 times, but, 3 SLCs next to each other could hold the same value.

    A linear growth of bits results in an /exponential/ growth of the value those bits, when combined, can represent. It doesn't matter if all those bits are from a single cell, or X number of cells. How you get bits doesn't matter.
  • Taracta - Monday, February 27, 2012 - link


    Did some research to see where you were coming from with the data you presented.


    gives some insight on TLC block sizes and why is doesn't follow the actual size of a TLC cell. Basically some pages and not use in TLC block configurations. Strangely the amount of pages in a TLC block is more than double that of a MLC block!

    I leave it up to you to clarify the article as it is somewhat confusing and needs some explanation of the differences between the cell, page and block sizes for TLC.
  • Kristian Vättö - Monday, February 27, 2012 - link

    Actually, TLC block size does (or at least should) follow the bits-per-cell idea. 25nm IMFT MLC NAND brought us 8KB pages and 256 pages per block. According to your link, TLC has 384 pages per block (i.e. 3*128 which means 128 pages per bit). MLC is now using that same 128 pages per bit idea (before it was 64 pages per bit).

    It's possible that TLC moved to a bigger block size before MLC and SLC because that lowers the cost and ultimately TLC is all about cost. There is need for less peripheral circuits between the blocks, which makes the die smaller and hence reduces production costs.


    I don't know what this has to do with your original point about the article being wrong, though. Of course, I'm happy to answer any questions regarding TLC, or at least give it a try (I haven't studied NAND technology in a university so e.g. that math stuff in your link is over my head).
  • mdshann - Monday, March 05, 2012 - link

    I haven't seen a 500 GB hard drive for anywhere near $50 in about 6 months now... where are you getting these drives? Right now the cheapest 500 GB drive on newegg.com is $84.99 and it's a bare Hitachi. Reply

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