Understanding TLC NAND
by Kristian Vättö on February 23, 2012 1:14 PM EST- Posted in
- Storage
- SSDs
- OCZ
- Indilinx Everest
- TLC
Our thoughts are a bit mixed. On the one hand, cheaper SSDs are exactly what consumers want. The performance is still there compared to hard drives, no matter what NAND is used. If you go to an Apple Store today and try out MacBook Air and Mac Pro, the MacBook Air will often feel faster, even though it's the slower Mac in terms of processing power. This is solely due to the presence of an SSD. An SSD can bring new life to a computer that is otherwise considered obsolete. That's why we think everyone would want an SSD, but it's understandable that the masses won't adopt SSDs until the price and capacities are reasonable. This is definitely where TLC shines—it provides us with noticeably cheaper SSDs, possibly cheap enough for the masses to adopt (e.g. well under $1 per GB).
On the other hand, we're concerned that the cut in prices is done at the expense of endurance. One advantage often heard about buying an SSD is that SSDs are a lot more reliable than hard drives. In terms of P/E cycles, that is probably true with current MLC NAND. However, there have been quite a few widespread firmware issues, such as SF-2281 BSOD and Intel 320 Series 8MB bugs. Those have been fixed, and we may finally be looking at SSDs which have good performance, adequate endurance, and are more or less trouble-free. However, TLC will require new controller logic, and new logic may result in additional firmware issues.
The earliest SSDs lacked performance, even though they were faster than most hard drives, especially in seek times. In just a few years, performance has increased exponentially, maybe even to a point where the average user won't notice the difference between the fastest SSD and a mediocre SSD.
Given the desire for performance, reliability, and cost, TLC NAND may take away one from the triplet: endurance. Notice we said "may", because P/E cycles aren't everything. It has been claimed that algorithms to minimize write amplification will follow Moore's Law, just like NAND does. In other words, every time there is a die shrink, wear leveling has been improved in order to keep endurance the same. On top of that, improvements in manufacturing technologies can keep the P/E count up as well. 20nm IMFT MLC is claimed to have 3000-5000 P/E cycles, just like 25nm IMFT MLC.
The good news is, MLC NAND will stay in production and hence MLC NAND based SSDs are not going anywhere. What TLC will provide is freedom of choice. If you use your computer for checking email and browsing the Internet, no doubt a TLC based SSD will be sufficient. For the majority of consumers, TLC SSDs should meet their demands.
In addition, the SSD market is evolving quickly; if you buy the best SSD today, it won't be the best for very long. Let's say that it lasts you for four years. In that time, the SSD market will change a lot—four years ago, we were looking at 16GB SSDs for nearly $600! By the time a typical SSD is ready for replacement, you will be looking at much faster SSD with more capacity, and likely for a lower price. In 4.5 years, we have gone from that 16GB offering with performance that often trailed behind contemporary HDDs to 120GB SSDs that are up to a couple orders of magnitude faster than HDDs on random access patterns (and still several times faster for sequential tranfers), all for a starting price of around $170. If that pattern holds for the next four years, we'll be looking at ~1TB SSDs in four years that offer transfer rates that would saturate multi-lane PCIe interfaces at even lower prices. While we expect the rate of progress to be quite a bit slower over the next four years, there's still plenty of room for improvements in SSD technology.
As far as TLC-based SSDs are concerned, all we can do now is to wait for the first product announcements to come. Once we get some review samples, we'll be sure to put them through our SSD test suite and see how they stack up to existing drives.
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aguilpa1 - Thursday, February 23, 2012 - link
I feel all warm and technical inside.Taft12 - Thursday, February 23, 2012 - link
"However, there have been quite a few widespread firmware issues, such as SF-2281 BSOD and Intel 320 Series 8MB bugs"No list of SSD firmware cockups is complete without mentioning the Kingston V200 abysmal write performance:
http://forum.notebookreview.com/solid-state-drives...
The fact that they're handing out V+ left and right to those requesting RMAs suggests to me the problem will never get fixed.
dorion - Thursday, February 23, 2012 - link
I'm having trouble understanding why the density gain from TLC is only linear and not quadratic. It seems like the web is crawling with a bunch of articles today saying the SLC -> MLC -> TLC density gain is 16 -> 32 -> 48. It should be 16 -> 32 -> 64. Am I right? Or is there something I'm not getting? Is it part of the ECC like Gray code?Death666Angel - Thursday, February 23, 2012 - link
Huh?SLC = 1 Cell, 1 bit
MLC = 1 Cell, 2 bits
TLC = 1 Cell, 3 bits
You seem to think that TLC is 1 Cell, 4 bits, which it is not. Not sure why you would think that, though.
JarredWalton - Thursday, February 23, 2012 - link
It's simple multiples, not powers. SLC stores one bit per cell, MLC is two, and TLC is three. MLC is thus twice the capacity of SLC, but TLC is only three times the capacity, not four. The power of two increase comes in the number of states to check: SLC checks two (0/1), MLC checks four (00,01,10,11), and TLC checks eight (000, 0001..., 110, 111). If someone were to try and do QLC they would need to check sixteen states, endurance would really plummet, and performance would be worse as well.dorion - Thursday, February 23, 2012 - link
I cant believe I overlooked the difference between bits you can store and how high you can count with a certain number of bits.ionis - Friday, February 24, 2012 - link
That only proves it should go 16->32->64.1 bit - 2 states - 16 Gb
2 bits - 4 states (double the previous) - 32Gb
3 bits - 8 states (double the the previous) - should be 64Gb not 48Gb. I'm still confused how the author got 48Gb.
JMC2000 - Friday, February 24, 2012 - link
The number of bits per cell is not equal to the number of voltage states. I'm not very knowledgeable in how NAND is produced, but I think the increase in voltage states by x2 per bit may have to do with the need for differentiation to write/erase each bit.ionis - Friday, February 24, 2012 - link
The article explicitly states that the number of bits per cell is equal to the number of voltage states.JMC2000 - Friday, February 24, 2012 - link
Do you mean this paragraph?"Rather than shrinking the die to improve density/capacity, TLC (like MLC) increases the number of bits per cell. In our SSD Anthology article, Anand described how SLC and MLC flash work, and TLC works the same way but takes things a step further. Normally, you apply a voltage to a cell and keep increasing it until you reach a point where the result is far enough from the "off" state that you now consider the cell as being "on". This is how SLC works, storing one bit per cell. For MLC, you store two bits per cell, which means instead of two voltage states (0 and 1) you have four states (00, 01, 10, 11). TLC takes that a step further and stores three bits per cell, or eight voltage states (000, 001, 010, 011, 100, 101, 110, and 111). We will take a deeper look into voltage states and how they work in the next page."
Or this one?
"SLC only has two program states, "0" and "1". Hence either a high or low voltage is required. When the amount of bits goes up, you need more voltage stages. With MLC, there are four states, and eight states with TLC. The problem is that the silicon oxide layer is only about 10nm thick and it's not immortal; it wears out every time it's used in the tunneling process. When the silicon oxide layer wears out, the atomic bonds break and during the tunneling process, some electrons may get trapped inside the silicon oxide. This builds up negative charge in the silicon oxide, which negates some of the the control gate voltage."
Nowhere in the article does it state that the number of bits per transistor is equal to the number of voltage states.