Weaknesses of TLC: One Degree Worse than MLC

In a perfect world, increasing the number of bits per cell sounds like a very easy way to increase capacities while keeping the prices down. So, why not put a thousand bits inside every cell? Unfortunately, there's a downside to storing more bits per cell.

Fundamentally, TLC shares the same problems as MLC when compared to SLC, but takes things one step further. Now that there are eight voltage levels to check, random reads will take more time: 100µs for TLC. That's four times longer than what it takes SLC to random read one bit, and twice as long as what it takes for MLC to complete the same task. Programming will also take longer, but unfortunately we don't have any figures for TLC yet.

Bits per Cell 1 2 3
Random Read 25 µs 50 µs 100 µs
Erase 2ms per block 2ms per block ?
Programming 250 µs 900 µs ?

On top of the decrease in performance, TLC also has worse endurance than MLC and SLC. Precise P/E cycle figures are not yet known, but we are most likely looking at around 1000 cycles. Hynix has a brief product sheet for their 48nm TLC flash, which has 2500 P/E cycles. At least in MLC flash, the move to 3Xnm halved the P/E cycles so we would be looking at 1250 cycles. 2Xnm brought even fewer cycles, roughly 3,000, and with same math we get 750 cycles for 2Xnm TLC. X-bit labs reported 1,000 cycles for TLC, which sounds fair. It's also good to keep in mind that endurance can vary depending on the manufacturer and maturity of the process. For example the first 25nm NANDs were good for only ~1,000 cycles, whereas today's chips should last for over 3,000 cycles.

  5Xnm 3Xnm 2Xnm
SLC 100,000



MLC 10,000 5,000 3,000
TLC 2,500 1,250


But why does NAND with more bits degrade quicker? The reason lies in the physics of silicon. To understand this, we need to take a look at our beloved Mr. N-channel MOSFET again.

When you program a cell, you are placing a voltage on the control gate, while source and drain regions are held at 0V. The voltage forms an electric field, which allows electrons to tunnel through the silicon oxide barrier from the N-channel to the floating gate. This process is called tunneling. The silicon oxide acts as an insulator and will not allow electrons to enter or escape the floating gate unless an electrical field is formed. To erase a cell, you apply voltage on the silicon substrate (P-well in the picture) and keep control gate voltage at zero. An electric field will be formed which allows the electrons to get through the silicon oxide barrier. This is why NAND flash needs to be erased before it can be re-programmed: you need to get rid of the old electrons (i.e. old data) before you can apply new electrons (i.e. new data).

But what does this have to do with SLC, MLC and TLC? The actual MOSFET is exactly the same in all three cases, but take a look at the table below.

SLC "0" High Voltage
"1" Low Voltage
MLC "00" High Voltage
"01" Med-High Voltage
"10" Med-Low Voltage
"11" Low Voltage
TLC "000" Highest Voltage
"001" High Voltage
"010" Med-High Voltage
"100" High-Medium Voltage
"011" Low-Medium Voltage
"101" Med-Low Voltage
"110" Low Voltage
"111" Lowest Voltage




SLC only has two program states, "0" and "1". Hence either a high or low voltage is required. When the amount of bits goes up, you need more voltage stages. With MLC, there are four states, and eight states with TLC. The problem is that the silicon oxide layer is only about 10nm thick and it's not immortal; it wears out every time it's used in the tunneling process. When the silicon oxide layer wears out, the atomic bonds break and during the tunneling process, some electrons may get trapped inside the silicon oxide. This builds up negative charge in the silicon oxide, which negates some of the the control gate voltage.

At first, erasing becomes slower because higher voltages need to be applied (and for a longer time) before the right voltage is found. Higher voltage causes more stress on the oxide, wearing it out even more. Eventually, erasing will take so long that the block has to be retired to maintain the performance. There is a side effect, though. Programming will be faster because there is already some voltage in the cell due to the electron trapping. However, the time won because of that is much smaller than the time it takes to erase the cell when more voltage pulses are required to erase the cell. That's why the block has to be retired when the wear level reaches a certain point.

Here comes the differerence between SLC, MLC and TLC. The fewer bits you have per cell, the more voltage room you have. In other words, SLC can tolerate more changes in the voltage states because it has only two states. In TLC, there are eight, so the margin for errors is a lot smaller.

Lets assume that we have an SLC NAND that takes voltage between 0V and 14V. To program the cell to "1", a voltage between 4V and 5V needs to be applied. Likewise, you need a voltage from 9V to 10V to program the cell to "0". In this scenario, there is 4V of "spare" voltage between the states. If we apply this example to MLC NAND, the spare voltage will be cut to half, 2V. With TLC, that spare value is only 0.67V if we use the same 1V per voltage state ideaology.

However, when the oxide wears out and a higher voltage is needed, the programming voltages go up. To use the SLC example above, you would now need a voltage between 4V and 6V to program the cell to "0". That means a 1V loss in the spare voltage. And here comes the difference. Since SLC has more spare voltage between the states, it can tolerate a higher voltage change until the erase will be so slow that the block needs to be retired. This is why SLC has a substantially higher P/E cycle count; you can erase and reprogram the cell more times. Likewise, TLC tolerates the least change in voltage states, so it has the lowest amount of P/E cycles.

A Brief Introduction to SSDs and Flash Memory Availability and Controller support


View All Comments

  • Kristian Vättö - Thursday, February 23, 2012 - link

    That's definitely a very interesting idea, I haven't actually thought about it. Maybe we will see something like that in the future. It should be feasible since we have products like Momentus XT. Reply
  • marraco - Thursday, February 23, 2012 - link

    That's what I was planning to write, so I agree, but it should be taken further: A weared out TLC cell should not be taken away by the controller/firmware. Instead it should be "degraded" to a MLC, and once it degrades, it should be used a s SLC. Reply
  • hechacker1 - Friday, February 24, 2012 - link

    While that's an interesting concept, you would have to over provision it even more to account for storage loss as it is unable to store as many bits. It would be easier to define at creation that some of the NAND would be MLC, and some TLC.

    With really large SSD's, I think the life of TLC will be pretty good simply because we'll have so much storage to work with.

    Imagine if you had a 1TB SSD, with a low 750 cycles. You could still potentially get around 750TB (minus amplification) of writes onto it.
  • xrror - Monday, February 27, 2012 - link

    Hah, I had this same thought also.

    What would be great fun (but a nightmare for OEMs to validate) is if you as a user could arbitrarily choose what "modes" to run the flash in.

    It'd also be ironic that as an SSD "wore out" it would drastically lose capacity but yet become faster while doing it ;p
  • ViRGE - Friday, February 24, 2012 - link

    It seems like this would play hell with wear leveling though. Even though you're trying to segregate (largely) static data into TLC NAND, you're still going to periodically write to TLC NAND and as such need to do wear leveling to keep from burning out a smaller number of the TLC NAND cells too soon. It seems like the need to wear level would largely negate the segregation of data. Reply
  • Mr. GlotzTV - Thursday, February 23, 2012 - link

    Since SLC, MLC & TLC are physically the same why not make the firmware dynamic?
    A new (empty) starts storing information as SLC, when more storage is needed saves it as MLC or TLC. To ensure good performance and a long life of the drive it should store frequently modified & temporary files as SLC, other things like movies and music (files where speed is not important and aren't modified a lot) should be stored as TLC.
    other thoughts:
    when a TLC cell is too worn change it to MLC and later to SLC!

    I know this would require a new very complex (and probably buggy) firmware. But are there any concepts or something?
  • jjj - Thursday, February 23, 2012 - link

    http://www.anandtech.com/show/4284/sandisktoshiba-... Reply
  • Mr. GlotzTV - Thursday, February 23, 2012 - link

    as far as I understood it is about removing DRAM and using some kind of pseudo SLC cache instead. Not exactly what I was thinking about but good to know anyway.
    THX for the link.
  • Kristian Vättö - Thursday, February 23, 2012 - link

    Interesting idea, though I'm not sure if it's possible. While SLC, MLC and TLC are physically the same (i.e. they consist of the same transistors), I'm not sure what kind of process needs to be used to turn a NAND array into MLC or TLC instead of SLC. I would guess that it's more than what a simple SSD controller can do.

    I can try to dig up more info on NAND manufacturing and hopefully it will shed some light to this. Either way, it does sound very complicated and the possibility of data loss is huge if the NAND type is changed during use (you can't really go from TLC to SLC without having a huge cache).
  • ckryan - Thursday, February 23, 2012 - link

    There is MLC-1, which is MLC which stores only 1 bit like SLC. It's almost as good as SLC, but I assume is much cheaper -- MLC is much cheaper than SLC (even if you're discarding half the capacity). I believe FusionIO uses this in some applications. Reply

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