Fat Pockets, Dense Cache, Bad Pun

Whenever Intel introduces a new manufacturing process the first thing we see it used on is a big chip of cache. The good ol’ SRAM test vehicle is a great way to iron out early bugs in the manufacturing process and at the end of 2007 Intel demonstrated its first 32nm SRAM test chip.

Intel's 32nm SRAM test vehicle

The 291Mbit chip was made up of over 1.9 billion transistors, switching at 4GHz, using Intel’s 32nm process. The important number to look at is the cell size, which is the physical area a single bit of cache will occupy. At 45nm that cell size was 0.346 um^2 (for desktop processors, Atom uses a slightly larger cell), compared to 0.370 um^2 for AMD’s 45nm SRAM cell size. At 32nm you can cut the area nearly in half down to 0.171 um^2 for a 6T SRAM cell. This means that in the same die area Intel can fit twice the cache, or the same amount of cache in half the area. Given that Core i7 is a fairly large chip at 263 mm^2 I’d expect Intel to take the die size savings and run with them. Perhaps with a modest increase to L3 cache size.

A big reason we’re even getting this disclosure today is because of how healthy the 32nm process is. Below we have a graph of defect density (number of defects in silicon per area) vs time; manufacturing can’t start until you’re at the lowest part of that graph - the tail that starts to flatten out:

Intel’s 45nm process ramped and matured very well as you can see from the chart. The 45nm process reached lower defect densities than both 65nm and 90nm and did it faster than either process. Intel’s 32nm process is on track to outperform even that.

Two Different 32nm Processes?

With Intel now getting into the SoC business (System on a Chip), each process node will now have two derivatives - one for CPUs and one for SoCs. This started at 45nm with process P1266.8, used for Intel’s consumer electronics and Moorestown CPUs and will continue at 32nm with the P1269 process.

There are two major differences between the CPU and SoC versions of a given manufacturing process. One, the SoC version will be optimized for low leakage while the CPU version will be optimized for high drive current. Remember that graph comparing leakage vs. drive current of 45nm vs. 32nm? The P1268 process will exploit the arrows to the right, while P1269 will attempt to push leakage current down.

The second difference is that certain SoC circuits require higher than normal voltages and thus you need a process that can tolerate those voltages. Remember that with a SoC it’s not always just Intel IP being used, there are many third parties that will contribute to the chips that eventually make their way into smartphones and other ultra portable devices.

The buck doesn’t stop here, in two more years we’ll see the introduction of P1270, Intel’s 22nm process. But before we get there, there’s a little stop called Sandy Bridge. Let’s talk about microprocessors for a bit now shall we?

The Manufacturing Roadmap Tick-Tock: U R Doin it Right
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  • Targon - Wednesday, February 11, 2009 - link

    For the CPU market, the problem is the ever growing amount of cache memory. Intel processors are designed with the large cache being their solution to improvements that AMD brings to the table.

    I suspect that Intel will have more trouble after this move to the new fab process because the difficulty in moving to a new process node grows at an exponential rate. We saw Intel hit a wall with the Pentium 3 line because they were not ready for a new process shrink at that point, so the P4 came out. When Intel got their process technology on track, the people at Intel could go back to the Pentium 3 design(with improvements) to release the Core and Core 2 Duo.

    There will come a time when an all new design will be needed in order to hold on to their lead, and that is when AMD will probably catch back up, if AMD can survive until then.
  • BSMonitor - Thursday, February 12, 2009 - link

    What an utter load of BS. Thanks fanboy.

    You get all that from wiki?
  • PrinceGaz - Wednesday, February 11, 2009 - link

    Even though my last three CPUs were all from AMD (they made sense at the time- K6-III/400, Athlon XP 1700+, Athlon 64 X2 4400+), I have to disagree with your comment about the improvements (presumably the integrated memory controller) which AMD brings to the table.

    With Core i7, Intel has effectively removed the one last technological advantage AMD had- faster memory access. The fact that Intel chips still tend to have larger L3 caches is quite simply because they can afford to give it to them, as they are ahead of AMD on the fab-process. For a high-end desktop chip where there is die-space to spare, you could add some more cores which will probably sit idle (keeping four busy is hard enough, especially with HT), but adding more L3 cache (so long as the latency of it is not adversely affected) is a very cheap and easy way to use up the space and provide a bit of a speedup in almost everything.

    AMD is currently fighting a losing game. The Phenom II (bug-fixed Phenom) cannot compete with Core i7 with AMDs current fabs, and unlike Intel who have the tick-tock steady new-process, then new-design with large teams working on each step; AMD seem to have one team working on a new design, which has to be made to work with whichever process looks like the best option at the time.

    We need AMD to survive for the x86 (or x64, who came up with that :p ) CPU market to be competitive, but I think the head of AMD is going to have to get into bed with the head of IBM, else they are doomed to fall ever further behind Intel in chip-design. The K10 is promising, but a long way off still, and AMD hasn't exactly been raking in the billions of dollars of profits recently to do that R&D. VIA have found an x86 CPU niche they can compete in, I fear that unless AMD pull an elephant out the hat with the K10, they'll have to slot in between VIA and Intel in providing CPUs specialising in a particular performance-sector, with Intel being the undisputed leader.
  • JonnyDough - Wednesday, February 11, 2009 - link

    Well said. I concur.

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