Core Tune-up

While the most significant sounding improvements were rolled into the SSE128 changes in Barcelona, they are merely the tip of the iceberg. The laundry list of improvements to Barcelona starts with the branch predictor.

In general, the accuracy of a CPU's branch predictor determines how wide and how deep of a design you can make. The average number of instructions before the predictor mispredicts governs how many instructions you can have in flight, which in turn controls how many execution units you can realistically keep fed on a regular basis. The K8's branch predictor was quite good and very well optimized for its architecture, but there were some advancements Intel introduced in the Pentium M and Pentium 4 that AMD could stand to benefit from.

Barcelona adds a 512-entry indirect predictor which, believe it or not, predicts indirect branches. An indirect branch is one where the target of the branch is a location pointed to by an address in memory, in other words, a branch with multiple targets. Instead of branching directly to a label indicated by the branch instruction, an indirect branch sends the CPU to a memory location that contains the location of the instruction that it should branch to.

Intel added an indirect predictor to its Pentium M processor based on the idea that the more you could limit the number of mispredicted branches, the more efficient your processor could be (thus lowering power consumption). The indirect predictor also made its way into Prescott in order to help minimize the performance deficit incurred by further pipelining the NetBurst architecture.

In Prescott, the simple addition of an indirect predictor resulted in over a 12% reduction in mispredicted branches in SPEC CPU2000. While details of how AMD and Intel differ in their predictor algorithms aren't public, we can expect similarly large improvements in areas where indirect branches are common. In the 253.perlbmk test of SPEC CPU2000 the reduction in mispredicted branches with Prescott was significant, reaching almost 55%. With Barcelona, fewer mispredicted branches means higher overall IPC and greater efficiency both from a power and performance standpoint. AMD doesn't have the incredibly deep pipeline to worry about that Intel did with Prescott, but the efficiency improvements should be significant.

The inclusion of an indirect predictor wasn't the only crystal ball improvement in Barcelona; the size of the return stack in the new core is double what it was in K8. In very deep call chains, for example code that calls many subroutines (e.g. recursive functions), the CPU will eventually run out of room to keep track of where it has been. Once it starts losing track of return addresses, it loses the ability to predict branches involved with those addresses. Barcelona helps alleviate the problem by doubling the size of the return stack. These sorts of improvements are generally implemented by profiling the behavior of software commonly used on a manufacturer's CPU, so we asked AMD what software or scenario drove this improvement of Barcelona. AMD wouldn't give us a concrete example of a situation other than to say that the return stack size improvements were made at the request of a "large software vendor".

The final improvement to the K8's branch prediction came through the usual channels - Barcelona now tracks more branches than its predecessor. There's no mystic science to branch prediction; a processor simply looks at branches it has taken and bases its predictions on historical data. The more historical data that is present, the more accurate a branch predictor becomes. When the K8 was designed it was built on a 130nm manufacturing process; with the first incarnation of Barcelona set to debut at 65nm AMD definitely has the die space to track more branch history data.

SSE128 Stacks and Loads of Optimizations
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  • johnsonx - Saturday, March 3, 2007 - link

    Actually that's the new Double-Dog-Dare RAM-3.
  • JarredWalton - Thursday, March 1, 2007 - link

    Crazy D's... they're like rabbits!
  • AkumaX - Thursday, March 1, 2007 - link

    Great read. I love Anand's articles. We'll see what the future holds, for both AMD and Intel
  • MAME - Thursday, March 1, 2007 - link

    I wonder how much market share AMD will lose until this chip become readily available.
  • tuteja1986 - Thursday, March 1, 2007 - link

    None... AMD will loose no marketshare. They are in bloody price war... Intel hasn't really regained any lost territory. But Intel have the advantage of performance is trying to find a breakthrough in AMD market share to retake back the lost territory. AMD is still selling everything they make but at huge looses caused by the price war.
  • Griswold - Thursday, March 1, 2007 - link

    Huge loses? Do you mistake the loss of Q406 due to the ATI purchase as a loss due to selling under production costs?
  • Phynaz - Thursday, March 1, 2007 - link

    Seen that AMD cach flow recently?
  • TwistyKat - Thursday, March 1, 2007 - link

    ...you have people like me who won't buy anything from Intel. If we didn't have AMD to make Intel competitive we would never have the range of choices we have today. We'd all be running monster Itanics with massive electricity bills.

    Intel has the resources to effectively put AMD out of business over time if it so chooses, and today I suspect they are focused on something close to that.


  • fitten - Thursday, March 1, 2007 - link

    quote:

    Intel has the resources to effectively put AMD out of business over time if it so chooses, and today I suspect they are focused on something close to that.


    Won't happen. In order to avoid anti-trust lawsuits, Intel will give AMD money to keep them afloat before they'll allow AMD to fail.
  • GoatMonkey - Friday, March 2, 2007 - link

    If AMD were to be purchased by a larger corporation, like IBM, it would leave Intel free to beat AMD down with all of their resources. Of course, at that point AMD would have the resources of IBM behind it and could potentially fight back better.

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