The Odd Multiplier Issue

Another item that was working against the Athlon 64 X2 5000+ on the previous page was the fact that it used an odd clock multiplier, in this case 13.0, in order to achieve its 2.6GHz clock speed. The problem with odd clock multipliers on AM2 CPUs is that the memory controller actually runs at DDR2-742 instead of DDR2-800. AM2 CPUs with even clock multipliers can run at DDR2-800 without any problems, and the reason why is pretty simple.

Below is the equation for calculating the memory speed of any Athlon 64 processor:

Reference Clock * Clock Multiplier = CPU Frequency

CPU Frequency / Memory Divisor = Memory Frequency

AMD only supports integer memory divisors, but let's start out by looking at how an AM2 CPU with an even clock multiplier fits the equation. For example, an Athlon 64 X2 4800+ runs at 2.4GHz and supports DDR2-800.

200MHz Reference Clock * 12x Clock Multiplier = 2400MHz CPU Frequency

2400MHz CPU Frequency / 6 = 400MHz DDR2-800 Memory Frequency

No problems, right? Now let's see how an odd clock multiplier changes things:

200MHz Reference Clock * 13x Clock Muliplier = 2600MHz CPU Frequency

2600MHz CPU Frequency / 6 = 433MHz DDR2-866 Memory Frequency

2600MHz CPU Frequency / 7 = 371MHz DDR2-742 Memory Frequency

See a problem? Because we can only use integer memory dividers, the only options for memory speed on a CPU with an odd clock multiplier are DDR2-866 or DDR2-742. Since AMD can't run above DDR2-800 spec, the only option is to underclock the memory to DDR2-742. This wasn't a problem on Socket-939 CPUs because DDR-400 ran at a 200MHz frequency, which you could always obtain by dividing the CPU clock frequency by an integer (since AMD never supported half multipliers). In fact, you simply used the same integer as the CPU multiplier. With DDR2-800, you need a 400MHz clock frequency, which you can only generate if you have an even CPU clock multiplier.

The problem gets even more complicated when you take into account the fact that Semprons and single-core Athlon 64s only support DDR2-667, which also has a similar issue.

While we haven't seen any significant downside to only running at DDR2-742 vs. DDR2-800, it is something to keep in mind when deciding what CPU to purchase. If you want your memory controller running at DDR2-800, you may want to stay away from the odd clock multiplier CPUs (X2 5000+, 4400+ and 4200+).

Athlon 64 X2 5000+: A Cheap FX or Overpriced 4800+? Power Consumption


View All Comments

  • Griswold - Tuesday, May 23, 2006 - link


    Okay, here's my guess for the stopgap solution...drum roll...L3 cache. I think AMD will release a 2.8 revised FX-62 with L3 cache or an ahead of schedule 3.0 GHz FX-64 with L3 cache. Just my guess.

    Sounds conceiveable indeed. Though, the latter option would probably blow TDP out of proportion on 90nm.
  • mlittl3 - Tuesday, May 23, 2006 - link

    Yeah, that is a problem but Anand did say "trick up its sleeve" so maybe they have one last 90 nm manufacturing process that's better than today's. I've read some articles about L3 cache coming for AMD and one article (take with grain of salt) that says AMD will ramp clock speeds fast. Maybe the trick will have something to do with these factors. Who knows? Reply
  • darkdemyze - Tuesday, May 23, 2006 - link

    Whatever it is I'm interested in reading about it Reply
  • Regs - Tuesday, May 23, 2006 - link

    Whatever it is, it's going to be expensive. Reply
  • TrogdorJW - Tuesday, May 23, 2006 - link

    Actually, I was sort of thinking that the "stopgap solution" might be to cut prices. God only knows that I would love to see a $200 X2 processor! Reply
  • Griswold - Tuesday, May 23, 2006 - link

    Well, they will have to drop prices at some point after core 2 is actually available. Reply
  • xFlankerx - Tuesday, May 23, 2006 - link

    Indeed, same results as expected. Maybe this will make the AMD fanboys shut up about "waiting to see what the final results are." NOTE: I have a AMD system, I'm simply addressing those that refuse to accept Conroe's superiority.

    Although...I must say that this "stop gap" solution by AMD has piqued my curiosity.

    But I believe that these say it perfectly;

    "One of its stipulations for sending out Socket-AM2 review kits was that the CPUs not be compared to Conroe."

    "We do get a sense of concern whenever Conroe is brought up around AMD."

    "So when Intel first started talking about its new Core architecture, we turned to AMD for a response that it surely must have had in the works for years, but as you all know we came up empty handed."

    Those just say it all for me. Seems like AMD's in trouble. From what I've been reading, K8L doesn't bring in architectural changes either. Sure you get Quad Cores, L3 cache, FB-DIMM support, DDR3, and faster HyperTransport, but if AMD doesn't improve on it's performance-per-clock efficiency, then Intel's Quad Cores (due almost 9 months before AMD's) are going to rule supreme yet again.
  • Griswold - Tuesday, May 23, 2006 - link


    Those just say it all for me. Seems like AMD's in trouble. From what I've been reading, K8L doesn't bring in architectural changes either.

    Maybe read up on it first.

    Memory mirroring, data poisoning, HT retry protocol support, doubled prefetch size (32byte instead of 16), 2x 128bit SSE units (instead of 2x 64bit), out of order load execution, Indirect branch predictors and a handful new instructions sure sounds like a few architectural changes and not just a simple revision stepping.
  • rADo2 - Tuesday, May 23, 2006 - link

    Sorry, links again:

    Intel Conroe @ 3.9GHz: SuperPI 1M - 12.984s">

    AMD FX-57 @ 4.2GHz: SuperPI 1M - 21.992s">
  • MadAd - Monday, May 29, 2006 - link

    Try measuring like for like and then come back with your silly benchmark comparison. EG use a superpi data size that will fit on BOTH cpus caches, not just conroes and then compare performance.

    With the FX57 having just a 1M cache its bullsht smoke and mirrors saying the 1M superpi is slower, o rly? perhaps thats because it takes more than 1M to hold both the feature and data sets on a 1M superpi.


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