Intel CPU Roadmap Update

We have a small update to the Intel desktop roadmap, and not much has really changed. Everything from our last update remains the same, and it's basically business as usual. So what's new? We'll start off with the most interesting area in our view, the dual core units. As usual, we'll highlight the updates and additions.

Intel Desktop Performance Roadmap
Processor Core Name Clock Speed Socket Launch Date
??? Conroe ??? ??? 2H'06
Pentium D >= 950 Presler ??? LGA 775 Q2'06
Pentium D 950 Presler 3.4 2x2MB LGA 775 Q1'06
Pentium D 940 Presler 3.2 2x2MB LGA 775 Q1'06
Pentium D 930 Presler 3.0 2x2MB LGA 775 Q1'06
Pentium D 920 Presler 2.8 2x2MB LGA 775 Q1'06

We already covered the arrival of the Presler Pentium D cores last month (and Smithfield has been available for a few months). The chips will be dual core 65nm parts with EM64T, VT, EIST, and XD. If you're not familiar with those acronyms, here's the recap:

  • EM64T adds 64-bit support and is the Intel equivalent of AMD64.
  • XD provides some protection against buffer overflow attacks, again matching up to AMD's NX (No-eXecute) technology.
  • VT stands for Virtualization Technology and provides hardware level support for running multiple OSes concurrently on a single computer.

As we mentioned in our recent AMD roadmap update, it was only possible to run multiple OSes concurrenty in the past through such third party tools as VMware, and the hardware support should increase the performance quite a bit. As with the other technologies mentioned, VT has an AMD counterpart, dubbed Pacifica. The remaining technology warrants further explanation.

EIST stands for Enhanced Intel Speedstep Technology, which allows the processors to throttle down to lower clock speeds and voltages when idle and thus conserve power. The version of EIST in the Presler core should be superior to that of the Smithfield core as it will also be available on the 2.8 GHz model. Current EIST on Pentium and Pentium D chips reduces the clock speed to 2.8 GHz, making it a useless feature for a chip that runs at 2.8 GHz by default. We don't have any specific details on the new EIST, but we hope that it will offer more benefits than a static clock speed and voltage reduction. Ideally, we'd like to see something like AMD's Cool and Quiet where all lower CPU multipliers are unlocked - that's what Intel has in their Pentium M chips as well. Overclockers in particular like to have such control; however, Intel may or may not offer that degree of tuning.

We have one new entry for a potentially faster Presler model: 960 running at 3.6 GHz is the most probable candidate, although whether or not Intel decides to release such a chip will depend on a variety of factors. The more interesting addition is Conroe, which will use Intel's next generation architecture. Details on what Conroe will bring to the table are scarce, but we would imagine that all the previously mentioned technologies will be present. The major change is that Conroe will not use the NetBurst architecture that has been used in the Pentium 4 (and derivatives) line.

For those that don't follow processors closely, here's a brief explanation on why this decision was made. The long pipeline of NetBurst has become a liability with clock speeds beyond 4 GHz producing a lot of heat. Increasing clock speeds have always created more heat, but now we're hitting the point where they begin to scale out of control. Rather than trying to find ways of dealing with 150W power levels (or perhaps even higher), Intel has designed a new architecture "from the ground up." Of course, they're not really starting over, as they'll be using elements of all of their previous designs, but Conroe will be enough of a change that it will have a new name.

Thinking About Conroe
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  • JarredWalton - Thursday, August 11, 2005 - link

    Which is why we say speculatively that it can go either way. 4-wide or 3-wide? I'd say it's 50-50 which one Conroe will be. What you say about HyperThreading is a good reason to pursue 4-wide, though. Take the current NetBurst HTT hack and make it into a more useful SMT design (like in POWER5 I think). Go with fully independent queues, maybe even split up caches. There's not that much point in going from a 1MB cache to 2MB cache IMO. Imagine HTT with each threading core getting its own 1MB L2 (that would be as fast as the Prescott L2 rather than the slower Prescott-2M L2).

    Combined with more execution units, you could potentially increase performance of the core by 50% or more in multitasking scenarios without having to go all the way for four independent cores. I mean, current HTT doesn't add more than 5% to the die size. A second core doubles the die size. Take an in-between approach and go with a 15% increase to get a robust SMT solution, and you can get most of the benefits of SMP with far fewer transistors, right?

    (Note: I am NOT a CPU designer, so maybe I'm totally wrong about what can and can't be done. The above sounds reasonable to me, however.) :)
  • snedzad - Wednesday, August 10, 2005 - link

    No, not at all. Next year won't produce massive turbulences in microprocessor market. We should better keep our eyes open for 2007, 'cause quad core is on the horizon.
  • Thatguy97 - Tuesday, June 16, 2015 - link

    and conroe changed the industry

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