TSMC this week announced a new fabrication process that is tailored specifically for high-performance computing (HPC) products. N4X promises to combine transistor density and design rules of TSMC's N5-family nodes with the ability to drive chips at extra high voltages for higher frequencies, which will be particularly useful for server CPUs and SoCs. Interestingly, TSMC's N4X can potentially enable higher frequencies than even the company's next-generation N3 process.

One of the problems that is caused by shrinking sizes of transistors is shrinking sizes of their contacts, which means increased contact resistance and consequent problems with power delivery. Various manufacturers use different ways of tackling the contact resistance issue: Intel uses cobalt contacts instead of tungsten contacts, whereas other makers opted to forming contacts using selective tungsten deposition technology. While these methods work perfectly for pretty much all kinds of chips, there are still ways to further improve power delivery for high-performance computing (HPC) designs, which are relatively immodest about the total about of power/voltage being used. This is exactly what TSMC did to its N4X node. But before we proceed to details about the new fabrication process, let us see what advantages TSMC promises with it. 

TSMC claims that its N4X node can enable up to 15% higher clocks compared to a similar circuit made using N5 as well as an up to 4% higher frequency compared to an IC produced using its N4P node while running at 1.2V. Furthermore – and seemingly more important – N4X can achieve drive voltages beyond 1.2V to get even higher clocks. To put the numbers into context: Apple's M1 family SoCs made at N5 run at 3.20 GHz, but if these SoCs were produced using N4X, then using TSMC's math they could theoretically be pushed to around 3.70 GHz or at an even higher frequency at voltages beyond 1.2V.

TSMC does not compare transistor density of N4X to other members of its N5 family, but normally processors and SoCs for HPC applications are not designed using high-density libraries. As for power, drive voltages of over 1.2V will naturally increase power consumption compared to chips produced using other N5-class nodes, but since the node is designed for HPC/datacenter applications, its focus is to provide the highest performance possible with power being a secondary concern. In fact, total power consumption has been increasing on HPC-class GPUs and similar parts for the last couple of generations now, and there is no sign this will stop in the next couple of generations of products, thanks in part to N4X.

"HPC is now TSMC's fastest-growing business segment and we are proud to introduce N4X, the first in the ‘X’ lineage of our extreme performance semiconductor technologies," said Dr. Kevin Zhang, senior vice president of Business Development at TSMC. "The demands of the HPC segment are unrelenting, and TSMC has not only tailored our ‘X’ semiconductor technologies to unleash ultimate performance but has also combined it with our 3DFabric advanced packaging technologies to offer the best HPC platform."

Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
  TSMC
N5
vs
N7
N5P
vs
N5
N5HPC
vs
N5
N4
vs
N5
N4P
vs
N5
N4P
vs
N4
N4X
vs
N5
N4X
vs
N4P
N3
vs
N5
Power -30% -10% ? lower -22% - ? ? -25-30%
Performance +15% +5% +7% higher +11% +6% +15%
or
more
+4%
or more
+10-15%
Logic Area

Reduction %

(Density)
0.55x

-45%

(1.8x)


-


-
0.94x

-6%

1.06x
0.94x

-6%

1.06x


-


?


?
0.58x

-42%

(1.7x)
Volume
Manufacturing
Q2 2020 2021 Q2 2022 2022 2023 H2 2022 H1
2024?
H1 2024? H2 2022

In a bid to increase performance and make drive voltages of over 1.2V possible, TSMC had to evolve the entire process stack.

  • First, it redesigned its FinFET transistors and optimized them both for high clocks and high drive currents, which probably means reducing resistance and parasitic capacitance and boosting the current flow through the channel. We do not know whether it had to increase gate-to-gate pitch spacing and at this point TSMC does not say what exactly it did and how it affected transistor density.
  • Secondly, it introduced new high-density metal-insulator-metal (MiM) capacitors for stable power delivery under extreme loads.
  • Thirdly, it redesigned back-end-of-line metal stack to deliver more power to transistors. Again, we do not know how this affected transistor density and ultimately die sizes.

To a large degree, Intel introduced similar enhancements to its 10nm Enhanced SuperFin (now called Intel 7) process technology, which is not surprising as these are natural methods of increasing frequency potential.

What is spectacular is how significantly TSMC managed to increase clock speed potential of its N5 technology over time. A 15% increase puts N4X close to its next-generation N3 fabrication technology. Meanwhile, with drive voltages beyond 1.2V, this node will actually enable higher clocks than N3, making it particularly good for datacenter CPUs.

TSMC says that expects the first N4X designs to enter risk production by the first half of 2023, which is a very vague description of timing, as it may mean very late 2022 or early 2023. In any case, it usually takes a year for a chip to proceed from risk production to high-volume production iteration, so it is reasonable to expect the first N4X designs to hit the market in early 2024. This is perhaps a weakness of N4X as by the time its N3 will be fully ramped and while N4X promises to have an edge in terms of clocks, N3 will have a major advantage in terms of transistor density.

Source: TSMC

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  • mode_13h - Saturday, January 1, 2022 - link

    At Super Computing 2019, wasn't phase-change liquid cooling all the rage?
  • TheinsanegamerN - Saturday, December 18, 2021 - link

    They could always use pockets of dead silicon, just dead space, to provide a cooling area that helps suck heat out of cores or clusters. Said dead silicon from disabling e cores makes alderlake somewhat easier to cool.
  • brucethemoose - Friday, December 17, 2021 - link

    This is exactly what desktop CPUs need, where clockspeeds at the voltage wall are king. And I guess AMD has no reason to skip it, seeing how the laptop lineup (where you don't necessarily want those crazy clocks) will use entirely different chips, assuming their current design pattern holds.

    I wonder if Intel's fab division will come out with something similar? Rocket Lake and Tiger Lake were already kinda bifurcated like that.

    Also, I wonder what the area cost is? Some accelerators (like GPUs) would scale well with extra area vs extra frequency, but the cost surely isn't 15%... right?
  • nandnandnand - Saturday, December 18, 2021 - link

    I wouldn't be surprised if we see AMD release products made at TSMC, GlobalFoundries (12LP+), and Samsung in the same year.
  • mode_13h - Saturday, January 1, 2022 - link

    > the laptop lineup will use entirely different chips, assuming their current design pattern holds.

    Haven't they already said that desktop CPUs will all have an iGPU, from Zen 4 onward? That basically unifies them with laptop & desktop APUs, potentially limiting the compute-only chiplets for workstations & servers.
  • twtech - Saturday, December 18, 2021 - link

    I wouldn't mind seeing a Threadripper made on this node.
  • Oxford Guy - Saturday, December 18, 2021 - link

    High-frequency trading, i.e. bots controlled by the rich controlling the stock market.
  • name99 - Saturday, December 18, 2021 - link

    Something I don't get. When TSMC calls this an HPC node, do they actually mean an AMD desktop node?

    Real HPC does not appear to chase GHz for the obvious reason that doing so generates crazy amounts of heat.
    Top500 #1, Fugaku, runs at 2.2GHz on TSMC N7.
    #2,#3 are POWER at 3.1GHz
    #4 is 1.45GHz (China)
    #5 is Epyc at 2.45 GHz

    etc etc

    I suspect that this is another example of marketing gone mad -- TSMC have what is actually a desktop-targeted node, which will be used by AMD and nV for devices that can ramp up to "excess" GHz on the desktop, but which has no relevance to "real" HPC (except perhaps, if this is the only node AMD target, so they will ship chips that could run at 5.2GHz to actually run at 3GHz in some supercomputer, or data warehouse).

    Am I wrong in this analysis?
  • BushLin - Saturday, December 18, 2021 - link

    Broadly speaking, Supercomputers are put together to solve a particular type of problem and things like configuration and interconnectivity will be specifically designed with that in mind, clock speeds will be tuned to find efficiency for the code which is likely to be the same across a huge cluster...
    HPC workloads are varied to the point that that no assumptions can be made about what clock speed gives the best total cost of ownership while delivering the compute power required.
    There will be plenty of customers for high frequency cores (not desktop level boost clocks as these are run 24/7 with high levels of utilisation) with access to >128GB ECC RAM.
  • mode_13h - Saturday, January 1, 2022 - link

    You can only meaningfully compare clock speeds between two CPUs with the same microarchitecture. Chip designers target a particular critical path, which then dictates clock speed, based on the properties of a particular manufacturing process. A chip designed to use a longer critical path won't clock as high as one designed to a shorter target, but would still potentially benefit just as much from a process like N4X.

    The EPYC 7H12 and the F-tier processors provide some evidence that some HPC & server customers indeed care about clock speed:

    https://www.anandtech.com/show/16778/amd-epyc-mila...

    Plus, have you seen how high Nvidia, AMD, and Intel are pushing the power consumption of their A100, MI200, and PVC, respectively?

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