Intel to Create RISC-V Development Platform with SiFive P550 Cores on 7nm in 2022
by Dr. Ian Cutress on June 22, 2021 9:01 AM EST
As part of SiFive’s announcements today, along with enabling SiFive IP on Intel’s Foundry Service offerings, Intel will be creating its own RISC-V development platform using its 7nm process technology. This platform, called Horse Creek, will feature several of SiFive’s new Performance P550 cores also being announced today, and will be paired with Intel’s DDR and PCIe IP technology.
On first reading into the press release, it isn’t 100% clear that Intel’s commentary discusses a platform with P550 as a host or as an add-in device: to quote Intel, ‘We are pleased to be a lead development partner with SiFive to showcase to mutual customers the impressive performance of their P550 on our 7nm Horse Creek platform’. Intel historically typically keeps its Creek family names, such as Boulder Creek, Cherry Creek, or Timber Creek, for socketed platforms - not for all-in-one embedded development platforms. Not only that, the wording makes it sound like we should consider a RISC-V core as an assistant core managing another part of a system.
However it would appear that Intel intends to make this a fully-featured development system, along similar lines to SiFive’s own HiFive Unmatched platform launched early this year. What makes this special is that Intel is committing to developing the SoC on its own 7nm process node, which provides a ‘simpler’ vehicle for Intel to test and ramp up its 7nm technology. This can be coupled with increasing interest in RISC-V development, and deploying a platform though Intel’s supply chain and distribution might have a far reach to put these in the hands of upcoming developers.
The new SiFive Performance P550 core at the heart of Horse Creek is SiFive’s highest performance processor to date, with the company quoting a SPEC2006int of 8.65 per GHz. It is a Linux-capable core, with full support for the RISC-V vector extension v1.0rc. It has a 13-stage triple-issue out-of-order microarchitecture with a private 32KB+32KB L1 cache and a private L2 cache (per core) The design supports four cores in a single cluster that can be paired up to 4 MB of shared L3.
The time scale for this platform coming to market is quite interesting. Despite Intel recently committed to bringing its 7nm to market in 2023 with the compute tile for its Meteor Lake processor as its first 7nm product, we’re being told that Horse Creek silicon will be ready in 2022, which would make Horse Creek its first 7nm product. For what it is worth, it’s unlikely that the Intel RISC-V solution is tile-based, but it might be easy enough to bring a small RISC-V chip development platform to market around then. The chip is likely to be small, so that might work in favor of its costs as well. A question does remain as to whether Intel’s involvement here is purely in the hardware, or whether there will be an Intel-based software stack to go along with it.
Related Reading
- Samsung to Use SiFive RISC-V Cores for SoCs, Automotive, 5G Applications
- SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP
- SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs
- SiFive Unveils Freedom Platforms for RISC-V-Based Semi-Custom Chips
- Western Digital’s RISC-V "SweRV" Core Design Released For Free
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lmcd - Tuesday, June 22, 2021 - link
Delusional to claim that the volume leader in multiple essential categories isn't "in this century."Spunjji - Wednesday, June 23, 2021 - link
Their statement is daft, but it's equally daft to cite sales volume when the claim was about technology levels.TeXWiller - Wednesday, June 23, 2021 - link
I'm thinking edge, embedded and government plays here. The EU (eventually) and India comes to mind. Additionally, a new generation of students in the US and maybe in other countries have been gaining their basics in the RISC-V world so there is the talent recruiting angle as well.FunBunny2 - Wednesday, June 23, 2021 - link
yet another load-store cpu (with countless layers of buffers/caches) and dram speed NVME just in sight. this makes sense? load-store made sense only when the speed differential was glacial. those days are numbered. yes, Intel didn't back up Optane with a processor that could really leverage App Direct mode. not to mention OS transaction support.never said it would be simple, but then it took quite a while for load-store to gain hegemony.
MetalPenguin - Thursday, June 24, 2021 - link
Even DRAM speed is still 2 orders of magnitude slower than L1 caches in modern CPUs. They are still going strong for a reason.mode_13h - Friday, June 25, 2021 - link
Yeah, FunBunny2's post is a lot to pick apart. I think most of us decided not to bother.As far as I can see, the only real alternative to load/store is computational memory, which is finally gaining some traction for AI. One approach is characterized by Samsung's compute-embedded HBM2, merging computation into the memory. The other would be how lots of AI accelerators have tons of on-die SRAM, which moves the data closer to the compute elements.
SarahKerrigan - Saturday, June 26, 2021 - link
So looking at what SiFive has actually announced, I don't think the P550 has vector support like the article says - though the lower-end P270 does (they've launched a couple of smaller vector-capable cores, including the X280, but still nothing at the high end.) Sifive explicitly states the P270 is a vector core everywhere they can, but doesn't say the same about P550 anywhere that I can find.Wilco1 - Saturday, June 26, 2021 - link
Yes I think you are right. That means it might be another year (late 2023, or 2024) before there will be an OoO RISC-V core with a vector extension... This also makes the area and performance claims even more dubious. Recent improvements in GCC mean the performance benefit of a vector unit is much higher than ever before.MetalPenguin - Sunday, June 27, 2021 - link
I think the mention of vector support was a mistake. But why would that make you doubt the area and performance numbers from SiFive's official material?The area comparisons were against the A75, which doesn't have SVE. Just two 64-bit NEON/FP pipes I believe. The P550 also has 64-bit FP support, and according to older Linley material on U84 it also had two 64-bit FP pipes (just no SIMD). Granted the A75 supports a larger variety of instructions, but the area comparison doesn't seem that unreasonable to me.
Wilco1 - Sunday, June 27, 2021 - link
SIMD units add significant area so comparing cores with/without isn't a fair comparison. SIMD units also improve performance in many popular benchmarks. Geekbench results for recently released HiFive Unmatched (which uses U74) are over 7 times slower than Raspberry Pi 4 (Cortex-A72).The U84 is claimed to be 3 times faster than U74, so do the math. Hence the claims of P550 (an improved U84 core) beating Cortex-A75 look extremely dubious.