At this year’s TSMC Technology Symposium, the company took the opportunity to update its customers and industry onlookers on the semiconductor manufacturer’s latest developments in regards to its newest technologies and manufacturing roadmaps. As part of a regular presentation, the foundry updated us on its status on it’s current leading-edge manufacturing technologies, the N7, N5 and their respective derivatives such as N6 and N5.

TSMC segregates their leading-edge manufacturing nodes into three product “families”: 7nm, 5nm and the upcoming 3nm manufacturing node. As many will have noted through a wide range of products over the last couple of years, TSMC’s 7nm node introduction and mass manufacturing starting in 2018 was a true tour de force for the foundry, carving out a significant leadership in the industry that the nearest competitors have been struggling to keep up with to this day.

To date, TSMC has shipped over 1 billion 7nm chips, and the 7nm family is regarded as being extremely mature, with the foundry now focusing on ramping up 5nm products and upcoming 3nm advanced nodes.

In terms of 7nm family capacity, starting in 2021 the yearly installed capacity is truly starting to slow down significantly as many customers migrate over to the more advanced process nodes.

Forecast capacity projections for 2021 only include a 14% increase in 7nm family capacity – starting a slow pace that’s likely to mimic the foundry’s capacity progression for the older 16nm process family.

Although many customers are shifting towards 5nm and below, the 7nm family will remain very significant for revenue, manufacturing capacity, and customer value. The N6 node is an evolutionary design of the previous N7 node variations and simplifies the manufacturing steps by introducing light usage of EUV layers.

What’s been extremely surprising to see is the rate of adoption of N6 and how it is replacing N7 manufacturing volume: In 4Q20 the N6 node only accounted for 15% of the whole 7nm family manufacturing capacity, while this is expected to reach 48-50% one year later by 4Q21. This means that as we’re speaking, we’re seeing a lot of new ramps of brand-new high-volume N6 products, which is quite interesting. The usual suspects would be vendors such as MediaTek and their newest Dimensity SoCs, but we’ve also seen Qualcomm reveal 6nm mid-range SoC designs such as the Snapdragon 778G. We’ve yet to hear about N6 production from PC or HPC vendors, but given the large volume ramp, one could very well imagine that there must be some new products in those industry sectors as well.

5nm Capacity to Quadruple by 2023 over 2020

TSMC’s 5nm process node has been in mass production since 2020, and notably powers hundreds of millions of new SoCs powering Apple’s A14 chips in the iPhone 12 series as well as the new M1 Mac chip. Although HiSilicon was a lead customer of TSMC at 5nm, TSMC had halted all production for the company last September due to trade restrictions. TSMC today updates that it has shipped 500k N5 wafers, which would roughly represent a few hundred million chips. While this lead to Apple essentially having sort of exclusivity for the N5 node in 2020, as more companies are starting to ramp up their 5nm products TSMC will need to ramp up a lot more production capacity, which the company is heavily investing in:

For the full year of 2021, TSMC expects to rapidly double on their 2020 wafer capacity, and further increasing that by 75% in 2022. By 2023 the company forecasts a quadrupling of the 2020 capacity, and that would still be before the company’s new 5nm Arizona manufacturing plant is scheduled to go online and add a further 20k wafers/month of capacity.

TSMC’s N5 ramp is going extremely well, and as reported back at last year’s Technology Symposium, has reached better yields than the 7nm family process technology nodes ever have. The company here largely points out to simplified manufacturing steps thanks to more extensive usage of EUV layers compared to its 7nm DUV and EUV nodes. In an industry where the competition is struggling to ramp up yields on the latest leading-edge nodes, this is truly an astonishing feat by TSMC which should further cement the foundry’s current dominance.

The foundry is well aware of this fact and proudly demonstrates its technical prowess through an extremely interesting metric: Although TSMC “only” has 50% of the worldwide EUV machine install base, the company actually represents 65% share of the cumulative shipped EUV wafers, meaning that it’s making much more effective usage of its install capacity.

TSMC states that it’s been using an in-house developed pellicle for its EUV nodes since 2019 and more extensively in 2020. In comparison, ASML and Mitsui Chemicals only had recently a few months ago announced that they’re only planning to start volume sales of their own pellicle in 2Q21, essentially right now at the time of this article (ASML has reached out to us to clarify that they've been shipping pellicles to customers in volume for two years - thousands of units from their own production lines, and that the deal with Mitsui is solely transferring that volume production line externally). TSMC doesn’t state any technical details of their in-house pellicle, but if the N5 yields are to be a sign of the results, then it must be an important part of TSMC’s current success at leading edge nodes.

The company also noted that it’s been continuously improving EUV mask lifetime – meaning the amount of time that a mask is useable before it has to be replaced or repaired, pointing out that it is forecasting that it will roughly catch up with DUV mask lifetimes in 2021. In other words, it means that up until now, EUV masks had notably worse lifetime that would result in less manufacturing throughput due to downtime.

N4: Small Optical Shrink of N5

TSMC’s N4 node is a rather straightforward migration path from N5, leveraging iterative improvements in the process.

The company states that N4 promises a 6% density improvement over N5, achieved through optical shrinks of the logic, std cell library improvements and design rule pushes for tighter area usage. It’s stated that we’ll be seeing lower manufacturing process complexity through the reduction of masks, although not detailing the exact changes.

N4 representing smaller iterative changes has the benefit that yields are essentially roughly picking up where N5 is currently tracking at. This fact, along with the simplified process complexity would largely indicate that the N4 could well represent a similar shift from N5 that N6 currently is undergoing over N7, with many customers shifting over the new improved node.

We'll be covering more about TSMC's 2021 Technology Symposium in the coming days as we get to write things up, including more details on N3 and future nodes such as N2 and beyond - so please stay tuned.

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  • shadowjk - Thursday, June 3, 2021 - link

    What he means is TSMC 5nm is only used to make tiny little electric scooter engines, and he's interested in seeing pickup truck engines made on 5nm. Reply
  • Valantar - Thursday, June 3, 2021 - link

    What? Apple has been using 5nm TSMC chips since the iPhone 12 launched, and are also using it for the M1. The A14 has been on sale for more than half a year, and has likely sold hundreds of millions of units. Reply
  • hechacker1 - Friday, June 4, 2021 - link

    I don't think the guy has seen the benchmarks yet where the A14/M1 spanks most of Intel in IPC and Performance per watt. In comparable workloads! He's living in bizarro world.

    AMD might have a chance it didn't have a massive IO die on an older process. But they are going for servers. Apple is going for your hand held device.
    Reply
  • mode_13h - Friday, June 4, 2021 - link

    > AMD might have a chance it didn't have a massive IO die on an older process.

    Their APUs don't. Those are monolithic.
    Reply
  • eek2121 - Tuesday, June 1, 2021 - link

    As other folks have mentioned, Intel 10nm = TSMC 7nm. TSMC 5nm = Intel 7nm. People wonder why Intel wants to rebrand… Reply
  • AdrianBc - Wednesday, June 2, 2021 - link

    Your equivalences are right about the component density, at least about the theoretical component density.

    In practice, even the SuperFin Intel 10 nm is significantly worse than the TSMC 7 nm.

    Even if the Intel 10 nm is supposed to have the same density, AMD can easily provide a 3 times larger cache memory at the same price.

    That is likely due to the Intel process having far more defects at a given chip size and to the failure of Intel to predict that their process will have so many defects, in order to switch earlier to multiple chip designs, like AMD did. So their good density does not matter if they cannot manufacture as many components on a chip as TSMC.

    The second problem for Intel is that their even their 10 nm SuperFin transistors are worse than the 7 nm TSMC transistors, so at identical number of active cores and identical power consumption the clock frequency is lower for Intel, or if the clock frequency is raised to match AMD, then the power consumption is higher.

    The only hope for Intel is the improved 10 nm process used for Alder Lake, which is expected to allow higher clock frequencies than the 7 nm TSMC process, while hopefully not having a worse energy efficiency.

    However, next year the competition will began to use the TSMC 5 nm process, so even if the Enhanced SuperFin process will be proven to be better than the TSMC 7 nm, it will not enjoy supremacy for a long time.
    Reply
  • zodiacfml - Wednesday, June 2, 2021 - link

    This!! After seeing the 8 core Tiger Lake reviews, it appears Intel's 10nm is inferior to TSMC 7nm Reply
  • duploxxx - Wednesday, June 2, 2021 - link

    there is a difference in core logic and cache logic density.... why is the internet always so mind stuck with aging marketing density figures...

    Intel original proposed density is nowhere near there final density, due to so many issues they had to adapt over and over again. So I would not bet that suddenly they can also deliver the 7nm on original target.
    Reply
  • zodiacfml - Wednesday, June 2, 2021 - link

    Intel could be behind the density thing to save face. I was just surprised Intel's 8 core Tiger Lake lags in efficiency vs months old Ryzen 5000 mobile, considering Intel has better IPC Reply
  • melgross - Wednesday, June 2, 2021 - link

    2023 Reply

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