Update 07/02: Albeit a couple of days later than expected, the PCI-SIG has announced this morning that the PCI Express draft 0.71 specification has been released for member review. Following a minimum 30 day review process, the group will be able to publish the draft 0.9 version of the specficiation, putting them on schedule to release the final version of the spec this year.


Originally Published 05/25
As part of their yearly developer conference, the PCI Special Interest Group (PCI-SIG) also held their annual press briefing today, offering an update on the state of the organization and its standards. The star of the show, of course, was PCI Express 6.0, the upcoming update to the bus standard that will once again double its data transfer rate. PCI-SIG has been working on PCIe 6.0 for a couple of years now, and in a brief update, confirmed that the group remains on track to release the final version of the specification by the end of this year.

The most recent draft version of the specification, 0.7, was released back in November. Since then, PCI-SIG has remained at work collecting feedback from its members, and is gearing up to release another draft update next month. That draft will incorporate the all of the new protocol and electrical updates that have been approved for the spec since 0.7.

In a bit of a departure from the usual workflow for the group, however, this upcoming draft will be 0.71, meaning that PCIe 6.0 will be remaining at draft 0.7x status for a little while longer. The substance of this decision being that the group is essentially going to hold for another round of review and testing before finally clearing the spec to move on to the next major draft. Overall, the group’s rules call for a 30-day review period for the 0.71 draft, after which the group will be able to release the final draft 0.9 specification.

Ultimately, all of this is to say that PCIe 6.0 remains on track for its previously-scheduled 2021 release. After draft 0.9 lands, there will be a further two-month review for any final issues (primarily legal), and, assuming the standard clears that check, PCI-SIG will be able to issue the final, 1.0 version of the PCIe 6.0 specification.

In the interim, the 0.9 specification is likely to be the most interesting from a technical perspective. Once the updated electrical and protocol specs are approved, the group will be able to give some clearer guidance on the signal integrity requirements for PCIe 6.0. All told we’re not expecting much different from 5.0 (in other words, only a slot or two on most consumer motherboards), but as each successive generation ratchets up the signaling rate, the signal integrity requirements have tightened.

Overall, the unabashedly nerdy standards group is excited about the 6.0 standard, comparing it in significance to the big jump from PCIe 2.0 to PCIe 3.0. Besides proving that they’re once again able to double the bandwidth of the ubiquitous bus, it will mean that they’ve been able to keep to their goal of a three-year cadence. Meanwhile, as the PCIe 6.0 specification reaches completion, we should finally begin seeing the first PCIe 5.0 devices show up in the enterprise market.

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  • Yojimbo - Wednesday, May 26, 2021 - link

    PCIe 5.0 is more important than PCIe 4.0 because CXL depends on it. For consumer applications the bus speed is not that important, but PCIe 4.0 was so late that it got to the point that the bus speed was becoming a bottleneck for consumers. Reply
  • p1esk - Wednesday, May 26, 2021 - link

    Not disputing that, but if in two years you have a choice to build something new with PCIe 5.0 or PCIe 6.0, why would you go with PCIe 5.0? Reply
  • mode_13h - Wednesday, May 26, 2021 - link

    > why would you go with PCIe 5.0?

    Because 6.0 will cost even more and burn even more power.
    Reply
  • CiccioB - Thursday, May 27, 2021 - link

    No, it won't.
    PCIe-6 is same speed as PCIe-5 but PAM4, that is 2 bit per clock instead on 1.
    So the power requirements will be almost the same but with double the bandwidth.

    It's the same technology Nvidia ha adopted for NVLink 3 a couple of years earlier.
    Probably because even PCI consortium has understood that it is not possible to continue pumping up the frequencies to go faster.

    PAM4 however means that the new standard is no more compatible with previous gen PICe, unless the controller has a fallback mode to PCIe-5.
    Reply
  • mode_13h - Saturday, May 29, 2021 - link

    > No, it won't.
    > PCIe-6 is same speed as PCIe-5 but PAM4, that is 2 bit per clock instead on 1.
    > So the power requirements will be almost the same but with double the bandwidth.

    You don't think PAM4 is more costly to implement and burns more power?

    It's definitely more noise-sensitive, meaning boards will have to use more layers and more expensive materials, as well as probably retimers (which will also be more expensive and consume more power, thanks to PAM4).

    > It's the same technology Nvidia ha adopted for NVLink 3 a couple of years earlier.

    That's only 50 Gbps and introduced just last year. Even on a RTX 3090, it doesn't hit PCIe 5.0 rates, much less PCIe 6.0.

    > PAM4 however means that the new standard is no more compatible with previous gen PICe

    Read the article. From one of the slides:

    "Maintains backward compatibility with all previous generations of PCIe architecture"
    Reply
  • mode_13h - Wednesday, May 26, 2021 - link

    > it got to the point that the bus speed was becoming a bottleneck for consumers.

    Not really. More like: "GPUs got to the point where they could *start* to reach the limits of PCIe 3.0". Go back and look at PCIe 3.0 SSDs and you won't see them even hit the link speed.
    Reply
  • Yojimbo - Thursday, May 27, 2021 - link

    I was talking about SSDs, not GPUs Reply
  • Yojimbo - Thursday, May 27, 2021 - link

    You don't think the release of SSDs faster than PCIe 3.0 speeds had something to do with a lack of market for them due to a lack of PCIe bandwidth? Reply
  • mode_13h - Saturday, May 29, 2021 - link

    > You don't think the release of SSDs faster than PCIe 3.0 speeds

    I think AMD releasing support for PCIe 4 created a scramble among SSD makers to try and build a product for it. But you could take most 1st-gen PCIe 4 SSDs and run them at PCIe 3 and hardly measure a difference.

    It's not at all like the situation we had with SATA SSDs, where they were link-limited for years.
    Reply
  • mode_13h - Wednesday, May 26, 2021 - link

    > looks like we are going to go straight from PCIe 4.0 to PCIe 6.0

    We're not. Sapphire Rapids and Alder Lake will use PCIe 5.0 this year or early next.

    We'll see when PCIe 6.0 hits. Whatever happens with 5.0, in the consumer space (and I speculate it will not be much), don't expect 6.0 to follow any time soon.
    Reply

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