Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510
by Andrei Frumusanu on May 25, 2021 9:00 AM EST- Posted in
- SoCs
- CPUs
- Arm
- Smartphones
- Mobile
- Cortex
- ARMv9
- Cortex-X2
- Cortex-A710
- Cortex-A510
The Cortex-A710: More Performance with More Efficiency
While the Cortex-X2 goes for all-out performance while paying the power and area penalties, Arm's Cortex-A710 design goes for a more efficient approach.
First of all, the new product nomenclature now is self-evident in regards to what Arm will be doing going forward- they’re skipping the A79 designation and simply starting fresh with a new three-digit scheme with the A710. Not very important in the grand scheme of things but an interesting marketing tidbit.
The Cortex-A710, much like the X2, is an Armv9 core with all new features that come with the new architecture version. Unlike the X2, the A710 also supports EL0 AArch32 execution, and as mentioned in the intro, this was mostly a design choice demanded by customers in the Chinese market where the ecosystem is still slightly lagging behind in moving all applications over to AArch64.
In terms of front-end enhancements, we’re seeing the same branch prediction improvements as on the X2, with larger structures as well as better accuracy. Other structures such as the L1I TLB have also seen an increase from 32 entries to 48 entries. Other front-end structures such as the macro-OP cache remain the same at 1.5K entries (The X2 also remains at 3K entries).
A very interesting choice for the A710 mid-core is that Arm has reduced the macro-OP cache and dispatch stage throughputs from 6-wide to 5-wide. This was mainly a targeted power and efficiency optimization for this generation, as we’re seeing a more important divergence between the Cortex-A and Cortex-X cores in terms of their specializations and targeted use-cases for performance and power.
The dispatch stage also features the same optimizations as on the X2, removing 1 cycle from the pipeline towards an overall 10-cycle pipeline design.
Arm also focuses on core improvements that affect the uncore parts of the system, which take place thanks to the new improvements in the prefetcher designs and how they interact with the new DSU-110 (which we’ll cover later). The new combination of core and DSU are able to reduce access from the core towards the L3 cache, as well as reducing the costly DRAM accesses thanks to the more efficiency prefetchers and larger L3 cache.
In terms of IPC, Arm advertises +10%, but again the issue with this figure here is that we’re comparing an 8MB L3 cache design to a 4MB L3 cache design. While this is a likely comparison for flagship SoCs next year, because the Cortex-A710 is also a core that would be used in mid-range or lower-end SoCs which might use much smaller L3 caches, it’s unlikely we’ll be seeing such IPC improvements in that sector unless the actual SoCs really do also improve their DSU sizes.
More important than the +10% improvement in performance is that, when backing off slightly in frequency, we can see that the power reduction can be rather large. According to Arm, at iso-performance the A710 consumes up to 30% less power than the Cortex-A78. This is something that would greatly help with sustained performance and power efficiency of more modestly clocked “middle” core implementations of the Cortex-A710.
In general, both the X2 and the A710’s performance and power figures are quite modest, making them the smallest generation-over-generation figures we’ve seen from Arm in quite a few years. Arm explains that due to this generation having made larger architectural changes with the move to Armv9, there has been an impact in regards to the usual efficiency and performance improvements that we’ve seen in prior generations.
Both the X2 and the A710 are also the fourth generation of this Austin microarchitecture family, so we’re hitting a wall of diminishing returns and maturity of the design. A few years ago we were under impression that the Austin family would only go on for three generations before handing things over to a new clean-sheet design from the Sophia team, but that original roadmap has been changed, and now we'll be seeing the new Sophia core with larger leaps in performance being disclosed next year.
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eastcoast_pete - Tuesday, May 25, 2021 - link
Would be great to see QC roll out new, ARM-based but home-made cores again; however, even if they do, the custom designs will most likely be big cores, which get paired with the 510s. But, maybe QC proves me wrong. That would be nice.nandnandnand - Tuesday, May 25, 2021 - link
"Because the new complex also only takes up a single interface on the DSU, it also opens up the possibility of designs larger than 8 “cores”, something I hope won’t happen, or hopefully only happens through more middle or big cores."Nah, I want a 24-core smartphone posthaste.
Kamen Rider Blade - Tuesday, May 25, 2021 - link
There's no point in putting 24-cores in a SmartPhone, other than to drain your battery faster.At the highest end, I think 12-cores in a Top of the line ARM CPU is enough for SmartPhone purposes with this configuration:
2x BIG; 8x Balanced; 2x little cores.
That would be enough for most power users to get everything they need out of their CPU's.
spaceship9876 - Tuesday, May 25, 2021 - link
It would be nice if they released a cortex-A35 successor as that is very old.nandnandnand - Tuesday, May 25, 2021 - link
Plus it could fulfill the efficiency role that A510 apparently fails at.mode_13h - Wednesday, May 26, 2021 - link
If they're going to continue with that product segment, then ARMv9 will virtually force them to.mode_13h - Tuesday, May 25, 2021 - link
Can anyone explain the color splotches in the floorplan plots? What are we supposed to glean from those?vvid - Wednesday, May 26, 2021 - link
>> Can anyone explain the color splotches in the floorplan plots?Each color marks specific unit: ALU, FPU, Instruction Decode, Branch predictor, Load/Store, etc
mode_13h - Thursday, May 27, 2021 - link
Thank you!Kamen Rider Blade - Tuesday, May 25, 2021 - link
So we went from ARM's big.LITTLEI prefer the BIG.little stylization.
to
BIG.Balanced.little as the new paradigm between ARM Core Types.