The Cortex-A710: More Performance with More Efficiency

While the Cortex-X2 goes for all-out performance while paying the power and area penalties, Arm's Cortex-A710 design goes for a more efficient approach.

First of all, the new product nomenclature now is self-evident in regards to what Arm will be doing going forward- they’re skipping the A79 designation and simply starting fresh with a new three-digit scheme with the A710. Not very important in the grand scheme of things but an interesting marketing tidbit.

The Cortex-A710, much like the X2, is an Armv9 core with all new features that come with the new architecture version. Unlike the X2, the A710 also supports EL0 AArch32 execution, and as mentioned in the intro, this was mostly a design choice demanded by customers in the Chinese market where the ecosystem is still slightly lagging behind in moving all applications over to AArch64.

In terms of front-end enhancements, we’re seeing the same branch prediction improvements as on the X2, with larger structures as well as better accuracy. Other structures such as the L1I TLB have also seen an increase from 32 entries to 48 entries. Other front-end structures such as the macro-OP cache remain the same at 1.5K entries (The X2 also remains at 3K entries).

A very interesting choice for the A710 mid-core is that Arm has reduced the macro-OP cache and dispatch stage throughputs from 6-wide to 5-wide. This was mainly a targeted power and efficiency optimization for this generation, as we’re seeing a more important divergence between the Cortex-A and Cortex-X cores in terms of their specializations and targeted use-cases for performance and power.

The dispatch stage also features the same optimizations as on the X2, removing 1 cycle from the pipeline towards an overall 10-cycle pipeline design.

Arm also focuses on core improvements that affect the uncore parts of the system, which take place thanks to the new improvements in the prefetcher designs and how they interact with the new DSU-110 (which we’ll cover later). The new combination of core and DSU are able to reduce access from the core towards the L3 cache, as well as reducing the costly DRAM accesses thanks to the more efficiency prefetchers and larger L3 cache.

In terms of IPC, Arm advertises +10%, but again the issue with this figure here is that we’re comparing an 8MB L3 cache design to a 4MB L3 cache design. While this is a likely comparison for flagship SoCs next year, because the Cortex-A710 is also a core that would be used in mid-range or lower-end SoCs which might use much smaller L3 caches, it’s unlikely we’ll be seeing such IPC improvements in that sector unless the actual SoCs really do also improve their DSU sizes.

More important than the +10% improvement in performance is that, when backing off slightly in frequency, we can see that the power reduction can be rather large. According to Arm, at iso-performance the A710 consumes up to 30% less power than the Cortex-A78. This is something that would greatly help with sustained performance and power efficiency of more modestly clocked “middle” core implementations of the Cortex-A710.

In general, both the X2 and the A710’s performance and power figures are quite modest, making them the smallest generation-over-generation figures we’ve seen from Arm in quite a few years. Arm explains that due to this generation having made larger architectural changes with the move to Armv9, there has been an impact in regards to the usual efficiency and performance improvements that we’ve seen in prior generations.

Both the X2 and the A710 are also the fourth generation of this Austin microarchitecture family, so we’re hitting a wall of diminishing returns and maturity of the design. A few years ago we were under impression that the Austin family would only go on for three generations before handing things over to a new clean-sheet design from the Sophia team, but that original roadmap has been changed, and now we'll be seeing the new Sophia core with larger leaps in performance being disclosed next year.

The Cortex-X2: More Performance, Deeper OoO The Cortex-A510: Brand-new Little Design Comes in Pairs
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  • Spunjji - Thursday, May 27, 2021 - link

    Comments saying "x86 is dead" are just as daft as the comments declaring that ARM will never be a threat to x86.
  • mode_13h - Tuesday, May 25, 2021 - link

    What a terrible naming scheme!

    If they didn't want to just start from a blank slate, they should've gone on to letters. So, A7A and A5A.

    Also, given that the X-cores are typically going to be paired with their cousin A-series core, the naming scheme should reflect that relationship. So, maybe the X1 should've been the X78 and the X2 could be the X710 or X7A.
  • mode_13h - Tuesday, May 25, 2021 - link

    Also, why skip 9? A59 and A79 would be a great mnemonic for the first mobile cores to be ARMv9!
  • nandnandnand - Tuesday, May 25, 2021 - link

    I'm fine with the naming scheme.

    For the Cortex-X line, they can just do X1, X2, X3, X4... X-cetera.

    For these new ones, A710 and A510 are the baseline, and they can put out A720, A525, or whatever until they run it up to A799. That could take over a decade if they don't increment the numbers so much. The '7' and '5' let you know these are related to the A78/A55, and the 3 digits lets you know it's part of the brave new world of ARMv9.
  • mode_13h - Tuesday, May 25, 2021 - link

    > they can put out A720

    That could potentially create some confusion about the relationship between A72 and A720.

    > 3 digits lets you know it's part of the brave new world of ARMv9.

    Okay, so create a new numbering scheme! No need to piggy back off the old one, if it's "a brave new world", right?
  • phoenix_rizzen - Tuesday, May 25, 2021 - link

    Would have been a good time to pick new letters. Leave Cortex-A, Cortex-X, Cortex-M etc for Armv8.x.

    Even better, drop the Cortex name, and pick something new for Armv9-based cores.

    X, Y, Z would have been nice for big, middle, little cores.

    Ah well, marketing-droids will do what marketing-droids do. :D
  • mode_13h - Tuesday, May 25, 2021 - link

    Also, A79 would line up nicely with being the last generation of this microarchitecture family.

    Then, maybe the "Sophia" cores could start a new numbering series.
  • GeoffreyA - Thursday, May 27, 2021 - link

    "What a terrible naming scheme!"

    They should battle it out with Intel's Marketing arm to see who's the best in the field of naming.
  • eastcoast_pete - Tuesday, May 25, 2021 - link

    Disappointed in the design choice of the new LITTLE cores. I have the strong suspicion that the IPC comparison of the 510 LITTLE core to the A73 (the 510 getting close to the A73) is with one 510 core per complex, maximal cache and cache bandwidth etc, which, of course, is highly theoretical. After all, the 510s are designed to come in pairs sharing resources for a reason. I am underwhelmed by this design, ARM's own power/perf curves show very little if any difference to A55 until one gets to the high end of the power curve, at which point the 710 big cores would have taken over. Unfortunately, Apple's power/perf crown for efficiency cores remains quite and comfortably safe. As an Android user, however, I remain stuck with ARM's designs, as none of the design houses (QC, Samsung) is even attempting custom core designs for smartphone SoCs. We are seeing the downside of a monopoly here
  • mode_13h - Tuesday, May 25, 2021 - link

    > I remain stuck with ARM's designs, as none of the design houses (QC, Samsung)
    > is even attempting custom core designs for smartphone SoCs.

    Qualcomm is saying they're using their Nuvia acquisition to make new mobile cores.

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