IBM Creates First 2nm Chipby Dr. Ian Cutress on May 6, 2021 6:00 AM EST
Every decade is the decade that tests the limits of Moore’s Law, and this decade is no different. With the arrival of Extreme Ultra Violet (EUV) technology, the intricacies of multipatterning techniques developed on previous technology nodes can now be applied with the finer resolution that EUV provides. That, along with other more technical improvements, can lead to a decrease in transistor size, enabling the future of semiconductors. To that end, Today IBM is announcing it has created the world’s first 2 nanometer node chip.
Names for Nodes
Just to clarify here, while the process node is being called ‘2 nanometer’, nothing about transistor dimensions resembles a traditional expectation of what 2nm might be. In the past, the dimension used to be an equivalent metric for 2D feature size on the chip, such as 90nm, 65nm, and 40nm. However with the advent of 3D transistor design with FinFETs and others, the process node name is now an interpretation of an ‘equivalent 2D transistor’ design.
Some of the features on this chip are likely to be low single digits in actual nanometers, such as transistor fin leakage protection layers, but it’s important to note the disconnect in how process nodes are currently named. Often the argument pivots to transistor density as a more accurate metric, and this is something that IBM is sharing with us.
Today’s announcement states that IBM’s 2nm development will improve performance by 45% at the same power, or 75% energy at the same performance, compared to modern 7nm processors. IBM is keen to point out that it was the first research institution to demonstrate 7nm in 2015 and 5nm in 2017, the latter of which upgraded from FinFETs to nanosheet technologies that allow for a greater customization of the voltage characteristics of individual transistors.
IBM states that the technology can fit ’50 billion transistors onto a chip the size of a fingernail’. We reached out to IBM to ask for clarification on what the size of a fingernail was, given that internally we were coming up with numbers from 50 square millimeters to 250 square millimeters. IBM’s press relations stated that a fingernail in this context is 150 square millimeters. That puts IBM’s transistor density at 333 million transistors per square millimeter (MTr/mm2).
|Peak Quoted Transistor Densities (MTr/mm2)|
|Data from Wikichip, Different Fabs may have different counting methodologies
* Estimated Logic Density
As you can tell, different foundries have different official names with a variety of densities. It’s worth noting that these density numbers are often listed as peak densities, for transistor libraries where die area is the peak concern, rather than frequency scaling – often the fastest parts of a processor are half as dense as these numbers due to power and thermal concerns.
With regards the movement to Gate-All-Around / nanosheet transistors, while not explicitly stated by IBM, images show that this new 2nm processor is using a three-stack GAA design. Samsung is introducing GAA at 3nm, while TSMC is waiting until 2nm. Intel by contrast, we believe, will introduce some form of GAA on its 5nm process.
IBM’s 3-stack GAA uses a cell height of 75 nm, a cell width of 40 nm, and the individual nanosheets are 5nm in height, separated from each other by 5 nm. The gate poly pitch is 44nm, and the gate length is 12 nm. IBM says that its design is the first to use bottom dieletric isolation channels, which enables the 12 nm gate length, and that its inner spacers are a second generation dry process design that help enable nanosheet development. This is complimented by the first use of EUV patterning on the FEOL parts of the process, enabling EUV at all stages of the design for critical layers.
Users might be wondering why we’re hearing that IBM is the first to a 2nm chip. IBM is one of the world’s leading research centers on future semiconductor technology, and despite not having a foundry offering of their own, IBM develops IP in collaboration with others for their manufacturing facilities. IBM sold its manufacturing to GlobalFoundries with a 10 year partnership commitment back in 2014, and IBM also currently works with Samsung, and recently announced a partnership with Intel. No doubt the latter two will be partnering with IBM on some level around this new development for its viability in their own production chain.
No details on the 2nm test chip have been provided, although at this stage it is likely to be a simplified SRAM test vehicle with a little logic. The 12-inch wafer images showcase a variety of different light diffractions, which likely points to a variety of test cases to affirm the viability of the technology. IBM says that the test design uses a multi-Vt scheme for high-performance and high-efficiency application demonstrations.
The chip was designed and made at IBM’s Albany research facility, which features a 100,000 sq. ft. clean room. The purpose of this facility is to build on IBM’s expansive patent and licensing portfolio for collaborations with partners.
We have a set of questions with IBM’s experts awaiting response. We also now have an active invitation to go visit, as and when we can travel again.
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Spunjji - Friday, May 7, 2021 - linkThanks for that analysis. I'm not sure I fully understood it, but I feel a little more informed for having read it!
Tams80 - Friday, May 7, 2021 - linkBut TSMC 5nm is roughly twice as dense TSMC 7nm.
The *performance* of the M1 is great, but it is not so far ahead that it shows node shrink advantage and an architecture advantage.
No doubt its performance is a mix of the two, but I doubt Apple's architecture design is that far ahead.
Anyway, there's no M1 on TSMC 7nm to compare it to.
michael2k - Friday, May 7, 2021 - linkYou can compare A14@5nm to A13@7nm. There is one less FP pipeline and the ROB is 70 entries smaller. There is a 10% clock boost and SPECInt shows an 18% performance increase. Therefore architectural changes account for about 8% of the performance difference. That also means the node change allows for a 10% clock boost at no power penalty. I would assume a 7nm M1 would clock at 90% of the 5nm M1
Abe Dillon - Saturday, May 15, 2021 - linkThe hypothetical density increase is 1.8x according to TSMC, but that doesn't necessarily translate to 1.8x increase in performance. Both of Apples 5nm chips come in at 133 MT/mm2 vs the 7nm A13 which comes in at 85 MT/mm2 means the real world increase is closer 1.5x.
If you want a more apples-to-apples comparison (pun intended) you can look at the A13 vs. the A14. I think someone found that the M1 cores emulate x86 code
Abe Dillon - Saturday, May 15, 2021 - link(sorry, hit send accidentally)
I think someone found the M1 cores emulate x86 cores as fast if not faster than an actual modern x86 core. I mean, node shrinks are great, but they aren't magic.
melgross - Thursday, May 6, 2021 - linkNo, their IP is better. Don’t you read the articles about their chips here?
name99 - Thursday, May 6, 2021 - linkThat's an absurd analysis that shows zero understanding of either Apple's micro-architecture or the large suite of power/performance techniques they have used at the circuit-level.
Kuhar - Friday, May 7, 2021 - linkAPPLE is the best company in the world they eat Intel and AMD and TSMC and Samsung for breakfast! Their chips are like 28 years ahead of AMD and they consume 0,00001 W of energy in a DAY. They talk to you and can read your mind and they make coffee while mining bitcoins. Besides that nVIDIA is going to close their business in 1 month because APPLE chips pwn them everywhere.
Spunjji - Friday, May 7, 2021 - link@Kuhar sarcastic exaggeration for satire only really works as a rebuttal if the other person *isn't* making a reasonable point.
Linustechtips12#6900xt - Monday, May 10, 2021 - linkThat hurt the few brain cells I have left after reading that, Jesus damn christ.