An Update on Turion

We also managed to corner some AMD folks about their new "mobile technology", the Turion 64. Here's what we were able to get out of them:

Much as we suspected, all of the power optimizations that went "into" Turion 64 are all transistor level optimizations.  Basically, selecting transistors that provide better thermal and power characteristics at the expense of lower switching frequencies.  Given that the Turion 64 runs at multiple speed grades lower than the fastest desktop Athlon 64s, this trade-off makes sense, but it also means that Turion 64 is no Pentium M killer.  There was one logic level optimization that went into Turion 64 and that was the support of a deeper C3 sleep state, but other than that, the Turion 64 is architecturally identical to a Socket-754 Athlon 64. 

The similarity between mobile and desktop goes one step further as we just confirmed that the packaging of the Turion 64 is no different than the Socket-754 desktop Athlon 64, except for the fact that the heatspreader is removed.  AMD did mention that they are looking at different packaging options that would surface in the second revision of the Turion 64 microprocessor. 

The Turion 64 notebooks that are going to be released will all be in the 1" - 1.4" thickness range, and weigh around 5 to 6.5 lbs.  The Turion is specifically targeted at what AMD is referring to as the mainstream thin and light segment, which also means that AMD will continue to remain non-competitive in the smaller form factor notebooks in which Centrino is available. 

AMD did mention that there is "focus" on a new mobile platform architecture, presumably similar in approach to the Centrino platform, designed from the ground up to be specifically for mobile applications rather than just down-scaling desktop technologies.  AMD was extremely quiet about details on this front other than the fact that it was something that their new Japan engineering lab is playing a key role in defining.  Whenever this new architecture does surface, it will carry the Turion brand.

Final Words

From talking to people like Justin Rattner and Fred Weber, the future of the CPU industry is looking to be particularly bright.  For the first time in recent history, we have both AMD and Intel agreeing on major points of future microprocessor architectures, and to AMD's credit, it looks like a lot of the decisions they made with the Athlon 64 were, in fact, the right ones.  What can we expect from AMD going forward?

We can expect the K8 execution core to remain relatively unchanged. Its successor may be deeper pipelined, but for the most part, the core itself appears to be mostly done evolving. 

We can expect future AMD chips, beyond 65nm, to be large groupings of cores, but the focus will continue to be on making them all general purpose, however with varying individual strengths (symmetric and heterogeneous). 

The Cell approach appears to be one supported by both AMD and Intel, but also appears to be too early in both their eyes.  It's clear that giving up Weber's symmetric heterogeneous approach isn't a sacrifice that either AMD or Intel are willing to make; they both appear to be waiting for smaller manufacturing processes to approach architectures similar in nature to Cell without sacrificing present day performance or hardware transparency. 

We also asked Weber about his thoughts on wafer and die stacking; he sounded particularly interested in them, but added that for a microprocessor, it's far too early to count on die stacking because of yield concerns.  He said that the time for the technology to be used on microprocessors would only exist once there's mass market use of it in memory manufacturing. Then, and only then, would it be mature enough to migrate to microprocessors. 

The K8 is here to stay


View All Comments

  • stephenbrooks - Thursday, March 31, 2005 - link

    I'm a bit confused by the terminology in places. Doesn't ILP mean "Instruction-Level Parallelism", i.e. that applies to distributing instructions between different execution units, and perhaps other tricks like out-of-order execution, branch prediction etc. But it certainly does NOT include "frequency", as seems to be implied by the first page! Unless it means that the longer pipeline will be interpreted as more parallelism (which is true). But that's not the only way to increase clock speed... a lot comes from the process technology itself. Reply
  • MrEMan - Thursday, March 31, 2005 - link

    I just realized that the link to "IDF Spring 2005 - Predicting Future CPU Architecture Trends" requires that you go to the next page, and not the one the link points to, and it is there where ILP/TLP is explained. Reply
  • MrEMan - Thursday, March 31, 2005 - link

    What exactly is ILP/TLP ? Reply
  • sphinx - Thursday, March 31, 2005 - link

    #12 PeteRoy

    I would have to agree with you.
  • Son of a N00b - Thursday, March 31, 2005 - link

    Great article Anand! I feel better informed and this was something that filled up my little spot of curiosity I had saved for the future of processors.

    It seems as if AMD will continue to keep up the great work. I will be a customer for a long time.
  • hectorsm - Thursday, March 31, 2005 - link

    blckgrffn I did not see your post until now. Your explanation seem to make a lot of sense. I guess is now a matter of opinion to how much is "30%" worth in terms of heat and transistor.

  • hectorsm - Thursday, March 31, 2005 - link

    Thanks Filibuster. The article confirms the up to 30% gain in processing power under certain multithreaded scenarios. But I am still confused to why this is a waste of resources specially when HT was design for multiple thread use.

  • blckgrffn - Thursday, March 31, 2005 - link

    The point of hyperthreading being a waste of resources is that it costs A LOT to put features like that into hardware, and the die space and tranistors used to do HT could probably have been used in better way to create a more consistent performance gain, or could have been left out all together, reducing the complexity, size, power use/heat output of the processor and putting a little bit more profit per chip sold at the same price into Intels pocket. That is why it is a misuse of resources.

  • BLHealthy4life - Thursday, March 31, 2005 - link

    Just release the FX57 already... Reply
  • hectorsm - Thursday, March 31, 2005 - link

    "not sure what you mean by "processing efficiency". all HT does is virtually separate the processor into two threads. maybe I'm missing something, but I can't figure out why everyone associates HT with performance gain. "

    There are supposedly fewer misprediction in the pipeline since there are two threads sharing the same pipes. Even when the total processing power is cut in halth, the sum of the two appears to be greater with HT. It has been reported up to 30% increase in total output when running two intances of folding@home and HT.

    So I am still wondering why Fred is calling it a "misuse of resources". Maybe he knows something we don't. It would be interesting to know more about this. Maybe someone at AnandTech get get a clarification from Fred?

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