Introduction

Just last week, we saw the first tests of Intel's newest Xeon processor formerly codenamed Irwindale. The major improvement Irwindale offers over Nocona is an extra 1MB of L2 cache. Our dual processor server configuration showed the 2MB cache of the Irwindale based Xeon offering a significant improvement under certain workloads. In a shared front side bus dual processor configuration, the improved cache hit rate of the 2MB Xeon helps to keep the NetBurst architecture from getting tangled up in the length of its pipeline when working with lots of data. As an added bonus, the impact of sharing a front side bus is softened when processors find more of the data they are looking for locally. On the consumer side, Intel's 600 series doesn't have to deal with shared busses or server sized workloads. Will the 2MB L2 cache still come through and offer a significant performance improvement?

The short answer is that consumer applications running on a single processor system don't see the same kind of benefit from a 2MB L2 as do server workloads running on a DP Xeon. There are areas where performance is affected, but this time around Intel is again refining and broadening its platform rather than simply scaling up speed and power. Let's take a look at the new offerings introduced this week.

First off we've got the new Pentium 4 600 series, launched in four models:

  Model  Clock Speed  Socket L2 Cache  FSB
Intel Pentium 4 660 3.6GHz LGA-775 2MB 800MHz
Intel Pentium 4 650 3.4GHz LGA-775 2MB 800MHz
Intel Pentium 4 640 3.2GHz LGA-775 2MB 800MHz
Intel Pentium 4 630 3.0GHz LGA-775 2MB 800MHz

What advantage does the Pentium 4 600 offer over the 500 series?  The main features are a 2MB L2 cache, Enhanced Intel SpeedStep Technology (EIST) and EM64T support (Intel's version of AMD's x86-64). The Pentium 4 600 is still built on the same 90nm process as the Pentium 4 500, it's just got twice the cache (which we'll talk about later). Features like EIST and EM64T support were always there on previous 90nm Pentium 4s, they were simply not enabled.

Currently the 500 and 600 series chips are priced to coexist with one another, first let's have a look at what Intel's official prices are:

   Pentium 4 500 Series  Pentium 4 600 Series
3.8GHz (Model _70) $637 Q2 Release
3.6GHz (Model _60) $417 $605
3.4GHz (Model _50) $278 $401
3.2GHz (Model _40) $218 $273
3.0GHz (Model _30) $178 $224

Then let's take a look at street prices for the chips using our RealTime Pricing Engine:

   Pentium 4 500 Series (street price)  Pentium 4 600 Series (street price)
3.8GHz (Model _70) $690 Q2 Release
3.6GHz (Model _60) $425 $635
3.4GHz (Model _50) $279 $429
3.2GHz (Model _40) $231 $295
3.0GHz (Model _30) $184 $257

The other thing to note is that the 500 series still holds the clock speed crown, with the 570J running at 3.8GHz, while the fastest 600 series is a 3.6GHz Pentium 4 660.  What we're seeing here is another example of Intel's move away from clock speeds as the only "improvements" from chip to chip.  We will however see a 3.8GHz Pentium 4 670 in Q2 of this year. 

Intel's next announcement is the move to a new 90nm core for the Pentium 4 Extreme Edition.  Until now, all EE chips have been based off of the old 130nm Northwood core, but with the move up to 3.73GHz the Extreme Edition actually uses the same 90nm core as the new Pentium 4 600 series.

Giving up its 2MB L3 cache in favor of a lower latency 2MB L2 cache, the new Extreme Edition only offers two benefits over the regular Pentium 4 600 series CPUs: clock speed and 1066MHz FSB support.  Priced at $999, the new Extreme Edition is priced in accordance with its name, as all of its predecessors have.

The new core, shared by both the Pentium 4 600 and the new Extreme Edition chips, is still built on the same 90nm process as the original Prescott, but thanks to the larger cache weighs in at 169 million transistors, an increase of 44 million (or 35%) over the original Prescott 1M core. 

There's a decent amount to discuss with this new core, so let's start at the biggest change - the cache.

Twice the Cache - 17% Higher Latency
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  • DerekWilson - Monday, February 21, 2005 - link

    you are correct mike (and you too mjz5)

    :-)
    Reply
  • DerekWilson - Monday, February 21, 2005 - link

    You're in luck -- Anand is writing that one personally. In my opinion he's the best there is at explaining technology so that anyone can understand it.

    And we've got "better" pics of cell, but they have boxes and text all over them to tell what block does what ... that's the best "clean" cell pic we've got.
    Reply
  • mjz5 - Monday, February 21, 2005 - link

    new news!! Nothing new from intel, actually that's not new news :-s... Reply
  • nourdmrolNMT1 - Monday, February 21, 2005 - link

    also, in the Cell picture, i count 8 cache areas, is there 8 sub processors with their own cache and then a main processor that controlls all the others with its own cache (the dark blue on the right, while the light blue is the sub processors cache?)

    MIKE
    Reply
  • nourdmrolNMT1 - Monday, February 21, 2005 - link

    :-)

    yea, find a better quality pic of the Cell processor. and please use small words that the small ppl like me can understand especially in the Cell article next week. i look forward to it, but dont want to be all confused like i am on a lot of your high tech articles.

    :-D

    MIKE
    Reply
  • DerekWilson - Monday, February 21, 2005 - link

    I can only fix 89 broken things at a time :-)

    anything else need tweaking?
    Reply
  • nourdmrolNMT1 - Monday, February 21, 2005 - link

    nvm post 3, read this post instead

    page 4 = bottom of page 3... fix it.

    I ORDER YOU NOW

    MIKE
    Reply
  • JustAnAverageGuy - Monday, February 21, 2005 - link

    It's fun to watch them add the pages one by one :) Reply
  • nourdmrolNMT1 - Monday, February 21, 2005 - link

    wrong graphs on page 4???

    MIKE
    Reply
  • AtaStrumf - Monday, February 21, 2005 - link

    He, he, no first post for all you first posters >;-) Reply

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