‘Better Yield on 5nm than 7nm’: TSMC Update on Defect Rates for N5
by Dr. Ian Cutress on August 25, 2020 9:30 AM EST
One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process.
The measure used for defect density is the number of defects per square centimeter. Anything below 0.5/cm2 is usually a good metric, and we’ve seen TSMC pull some really interesting numbers, such as 0.09 defects per square centimetre on its N7 process node only three quarters after high volume manufacturing started, as was announced in November at the VLSI Symposium 2019. As it stands, the defect rate of a new process node is often compared to what the defect rate was for the previous node at the same time in development. As a result, we got this graph from TSMC’s Technology Symposium this week:
As it stands, the current N5 process from TSMC has a lower defect density than N7 did at the same time in its development cycle. TSMC. This slide from TSMC was showcased near the start of the event, and a more detailed graph was given later in the day:
This plot is linear, rather than the logarithmic curve of the first plot. This means that TSMC’s N5 process currently sits around 0.10 to 0.11 defects per square centimeter, and the company expects to go below 0.10 as high volume manufacturing ramps into next quarter.
Part of what makes 5nm yield slightly better is perhaps down to the increasing use of Extreme UltraViolet (EUV) technology, which reduces the total number of manufacturing steps. Each step is a potential chance to decrease yield, so by replacing 4 steps of DUV for 1 step of EUV, it eliminates some of that defect rate.
TSMC’s first 5nm process, called N5, is currently in high volume production. The first products built on N5 are expected to be smartphone processors for handsets due later this year.
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- Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020
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vladx - Tuesday, August 25, 2020 - link
Jeezus you AMD fanbois are nutsliquid_c - Wednesday, August 26, 2020 - link
Right? The wishfull thinking and their whole “logic” is annoying the living hell out of me. AMD this, TSMC that. It’s a bussiness and money, not AMD, has the last word.Spunjji - Wednesday, August 26, 2020 - link
@liquid_c - it's not *just* about money. Money is a huge factor, yes, but it's not the only one.It's abundantly clear that most Intel shills (yeah, nice "AMD fanboi" projection from you and vladx) would be shit at running a business.
melgross - Tuesday, August 25, 2020 - link
No, they’re not. They’re AMD’s competitor. TSMC is really just a jobber.melgross - Wednesday, August 26, 2020 - link
It’s amazing that people only seem to get out of statements what they want to. Intel said that CPUs would not be fabled, but some other chips likely would be. Nobody knows what the future will hold, but we can only go by what we’re told. It would be good to keep that in mind.Spunjji - Wednesday, August 26, 2020 - link
Not really. Not without pissing off their shareholders."Please tell us again why you spent billions on fabs and then paid hugely over the odds for 3rd party fab access?"
TheReason8286 - Tuesday, August 25, 2020 - link
I dont understand why people are still saying this and especially with the 10nm comparison to 7nm. The reason Intel cant get their nodes right is because they were over-ambitious. Thus they've had to lower their ambitions and tone it down. For example their revised 10nm no longer appears to be similar to TSMC 7nm because they had to tone it down for it to actually yield anything worthwhile. So im very skeptical of their 7nm being similar to TSMC 5nm. Whose to say their 7nm wont be scaled down due to certain difficulties/delays.. I'm just really skeptical about Intel and their claims these daysWaltC - Tuesday, August 25, 2020 - link
Yes, until Intel can put its products where its mouth is there is little point in listening to them at all, imo.Spunjji - Wednesday, August 26, 2020 - link
Those people are just copy-pasting the same logic that used to apply to Intel's 32nm and 22nm nodes, whether it be through ignorance or a calculated appeal to the ignorance of others.I'll be interested to see what density and performance looks like on TGL when it finally releases - I'm curious as to whether this "superfin" stuff they're bragging about came at the expense of density. That would rely on them being honest about transistor count, though...
RobertMontefore - Tuesday, August 25, 2020 - link
And now Intel is looking for someone else (TSMC?) to fabricate their chips.