One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process.

The measure used for defect density is the number of defects per square centimeter. Anything below 0.5/cm2 is usually a good metric, and we’ve seen TSMC pull some really interesting numbers, such as 0.09 defects per square centimetre on its N7 process node only three quarters after high volume manufacturing started, as was announced in November at the VLSI Symposium 2019. As it stands, the defect rate of a new process node is often compared to what the defect rate was for the previous node at the same time in development. As a result, we got this graph from TSMC’s Technology Symposium this week:

As it stands, the current N5 process from TSMC has a lower defect density than N7 did at the same time in its development cycle. TSMC. This slide from TSMC was showcased near the start of the event, and a more detailed graph was given later in the day:

This plot is linear, rather than the logarithmic curve of the first plot. This means that TSMC’s N5 process currently sits around 0.10 to 0.11 defects per square centimeter, and the company expects to go below 0.10 as high volume manufacturing ramps into next quarter.

Part of what makes 5nm yield slightly better is perhaps down to the increasing use of Extreme UltraViolet (EUV) technology, which reduces the total number of manufacturing steps. Each step is a potential chance to decrease yield, so by replacing 4 steps of DUV for 1 step of EUV, it eliminates some of that defect rate.

TSMC’s first 5nm process, called N5, is currently in high volume production. The first products built on N5 are expected to be smartphone processors for handsets due later this year.

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  • RobertMontefore - Tuesday, August 25, 2020 - link

    Unless AMD has this weird piece of paper called a "contract." Reply
  • vladx - Tuesday, August 25, 2020 - link

    Fab contracts last only 2 years at most, after which AMD needs to renegotiate at which point Intel can just pay more. Reply
  • TimSyd - Tuesday, August 25, 2020 - link

    Really unlikely to happen. TSMC & AMD work well together & TSMC isnt likely to shaft a major customer like that. Bad form, bad precedent for other customers & not the way they do business.
    Fastest way to encourage your customers to get serious abt spending money to help Samsung/UMC or GF get in the game is to shaft them publicly.
    It *will* mean TSMC can push AMD higher on wafer pricing because they can use the Itel wafer allocation as a bargaining chip in the next round of pricing contract. Now that is much more TSMC's style.
    Reply
  • Guspaz - Tuesday, August 25, 2020 - link

    TSMC has already said that they see Intel as a short-term partner (a "rescuer", they said, where Intel would make some big orders and then drop them when their own fabs get back on track). Even if Intel offered more money for capacity, I really doubt they'd shortchange a long-term customer to satisfy a short-term one.

    TSMC is already production constrained. Their existing customers will use up as much fab capacity as they can build. They're not desperate for more business.
    Reply
  • Spunjji - Wednesday, August 26, 2020 - link

    Today in the Intel shill fantasies: every company works exactly the way they think a company should work in theory. Reply
  • Teckk - Wednesday, August 26, 2020 - link

    Yes, Intel will spend billions on it's fabs and spend more money to secure wafers from TSMC. Ever thought of the impact on gross margins and profitability?
    I hope Intel gets back on track but come on, don't be such a shill.
    Reply
  • TheReason8286 - Tuesday, August 25, 2020 - link

    The things people say... Like you literally should've thought about that before you decided to type that. Why would they care about Intel their main competitor and their chip woes to allow them to leapfrog a consistent customer in AMD who will be with them for the long run. Like someone said its not about money in this situation. Besides AMD already secured wafers for 7nm and 5nm as from what I heard TSMC is making AMD 5nm more specifically tuned to their architecture. Reply
  • melgross - Tuesday, August 25, 2020 - link

    Intel isn’t really a competitor. Samsung is a competitor. Intel produces their own chips, and just does a small fab business, while Samsung has a much bigger fab business. TSMC is entirely a fab business. Reply
  • vladx - Tuesday, August 25, 2020 - link

    Exactly, Intel fabs were never TSMC competitors since Intel doesn't make ani 3rd party products at their fabs. Reply
  • Gigaplex - Tuesday, August 25, 2020 - link

    If customers buy Intel chips fabbed by Intel vs buying AMD chips fabbed by TSMC, then yes, Intel is effectively a competitor. Reply

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