One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process.

The measure used for defect density is the number of defects per square centimeter. Anything below 0.5/cm2 is usually a good metric, and we’ve seen TSMC pull some really interesting numbers, such as 0.09 defects per square centimetre on its N7 process node only three quarters after high volume manufacturing started, as was announced in November at the VLSI Symposium 2019. As it stands, the defect rate of a new process node is often compared to what the defect rate was for the previous node at the same time in development. As a result, we got this graph from TSMC’s Technology Symposium this week:

As it stands, the current N5 process from TSMC has a lower defect density than N7 did at the same time in its development cycle. TSMC. This slide from TSMC was showcased near the start of the event, and a more detailed graph was given later in the day:

This plot is linear, rather than the logarithmic curve of the first plot. This means that TSMC’s N5 process currently sits around 0.10 to 0.11 defects per square centimeter, and the company expects to go below 0.10 as high volume manufacturing ramps into next quarter.

Part of what makes 5nm yield slightly better is perhaps down to the increasing use of Extreme UltraViolet (EUV) technology, which reduces the total number of manufacturing steps. Each step is a potential chance to decrease yield, so by replacing 4 steps of DUV for 1 step of EUV, it eliminates some of that defect rate.

TSMC’s first 5nm process, called N5, is currently in high volume production. The first products built on N5 are expected to be smartphone processors for handsets due later this year.

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  • Spunjji - Wednesday, August 26, 2020 - link

    We'll see. Between gains from architectural changes and N7P, RDNA 2 should be in a better position to compete with Nvidia than RDNA was.

    A lot depends on whether or not the rumours of Ampere being built on Samsung 8nm are true, though, along with how competitive that process actually is.

    Also, AMD do build CPUs too... and APUs. Those are going to rock on 5nm with mature DDR5 speeds.
  • TristanSDX - Wednesday, August 26, 2020 - link

    do not this so. Defect rate may only increase profits, and TSMC will eat it completely (good yield -> higher price / wafer for AMD)
  • WaltC - Tuesday, August 25, 2020 - link

    You're only talking about single-core boost frequencies--by design.
  • Anymoore - Wednesday, August 26, 2020 - link

    EUV has more stochastic fuzziness actually.
  • plopke - Tuesday, August 25, 2020 - link

    ..., so my replacing 4 steps of DUV for 1 step of EUV, ... tiny typo :)?
  • RobertMontefore - Tuesday, August 25, 2020 - link

    No one proofreads these days; the role of an editor has been relegated to a spell checker.
  • bji - Tuesday, August 25, 2020 - link

    Actually, it's been delegated to the readers.
  • shabby - Tuesday, August 25, 2020 - link

    Intel: oh yeah? Well we have better yield on 14nm than on 10nm... higher is better!
  • RobertMontefore - Tuesday, August 25, 2020 - link

    Intel is trying (er, WAS trying) to stay "in house" on their fabrication; didn't work out as they planned
  • psychobriggsy - Tuesday, August 25, 2020 - link

    Looks like 7nm didn't really get any better than the 0.09 figure for a long time, the first graph shows an improvement starting at Q6 and getting below 0.09 by Q8, but the second graph doesn't go beyond that (but shows good figures for N7+/N6).

    Also I thought TSMC were not going to use N7+ name any longer, yet there it is on that first graph.

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