Development of new fabrication technologies never stops at leading-edge companies such as TSMC. Therefore, it is not surprising to hear the annoucement that development of TSMC’s 3nm node is well underway, something the company publicly confirmed last week. As it appears, the manufacturing technology is out of its pathfinding mode and TSMC has already started engaging with early customers.

“On N3, the technology development progress is going well, and we are already engaging with the early customers on the technology definition,” said C.C. Wei, CEO and co-chairman of TSMC, in a conference call with investors and financial analysts. “We expect our 3-nanometer technology to further extend our leadership position well into the future.”

Since its N3 technology is in its early stages of development, TSMC doesn't currently talk about the specific characteristics of the process nor its advantages over N5. TSMC said that it had evaluated all possible transistor structure options for 3nm and came out with ‘a very good solution’ for its clients. The specification is under development and the company is confident it would meet requirements of its leading partnering customer.

One of TSMC’s arch-rivals, Samsung Foundry, plans to use nanosheet-based Gate-All-Around MBCFET transistors for its own 3nm (3GAAE) process technology. Since TSMC will have to be competitive with its rival, we expect the company to also advance its 3nm node significantly in comparison to its 5nm node. In fact, TSMC confirms that N3 is a brand-new process technology, not an improvement or iteration of N5.

Meanwhile, it is safe to say that that TSMC’s 3 nm node will use both deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography equipment. Since TSMC’s N5 uses up to 14 EUV layers, it is likely that N3 will go even higher in the amount of layers employed. The world’s largest contract maker of semiconductors also seems to be quite happy with its EUV progress and considers the technology important for its future.

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Source: TSMC

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  • rocky12345 - Tuesday, July 23, 2019 - link

    So my question is what are all these companies going to do when they reach 1nm nodes and have no where left to go. That day is coming up pretty fast if they are already talking 3nm node. Reply
  • rocky12345 - Tuesday, July 23, 2019 - link

    just to add in here. No wonder Intel has stuck with 14nm+++++++ for so long they finally learned getting to 1nm doe snot make them the winners in this race and there is the fact they are having problems with 10nm....lol Reply
  • rocky12345 - Tuesday, July 23, 2019 - link

    Did not mean to type doe snot supposed to be ""does not"". Reply
  • HardwareDufus - Tuesday, July 23, 2019 - link

    Doe Snot. That has been Intel's problem all along... They aren't using enough Doe Snot.... In their push to shrink the nodes, there isn't sufficient space for the required quantities of Doe Snot. Reply
  • HardwareDufus - Tuesday, July 23, 2019 - link

    Buck Snot was disqualified from most processes around the 28nm node shrinks. Reply
  • drexnx - Tuesday, July 23, 2019 - link

    right, that's what PDSOI stood for, Partially Doe Snot On Insulator,

    too bad FDSOI (Fawn & Doe Snot On Insulator) never got any traction
    Reply
  • Ashinjuka - Tuesday, July 23, 2019 - link

    OMG i am dying this is the best, simplest, funniest typo in this context Reply
  • ksec - Tuesday, July 23, 2019 - link

    I still remember a few years ago I posted TSMC 5nm in 2020 on Anandtech Forum and got stabbed front and back. Luckily I got someone with great reputation to back me up.

    3nm is looking like 2021, 3nm+ / 2nm in 2022, 2nm / 1nm in 2023, Possibly 1nm in 2024.

    Remember all these Node Number are marketing numbers. It is because someone started these number marketing TSMC had no choice but to follow suit. So there could be a few more nodes below 1nm.

    As the article have stated, 3nm is in development. I don't even doubt we could reach 2nm and 1nm. The problem isn't even technical, it is the unit economics. Even Apple only ships around 100M leading node SoC per year. Somewhere post 5nm / 3nm the design cost could be a limiting factor.

    So we have at least 5 years to go to figure out where we go next, that is from new material or stacked silicon.
    Reply
  • Death666Angel - Tuesday, July 23, 2019 - link

    "isn't even technical, it is the unit economics"
    Most things that are "proven to be technically possible" are hindered by absurd economic propositions.
    Reply
  • rahvin - Tuesday, July 23, 2019 - link

    From what I've read on the science of this there is going to be a hard limit on the trace size just like they've already encountered on the transistor size due to the quantum effects at this scale.

    To move beyond this limit they will probably have to move away from Silicon or start looking toward moving away from either binary or digital computing to advance. There was a very good recent article on using trenary (or trinary if you prefer) on current microprocessor being a pretty easy thing to adapt current process tech to.

    The move from binary to trenary would significantly expand the computer power. Even if this doesn't come to fruition when we hit those quantum limits on process tech, the only way forward will be a completely different path.
    Reply

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