Cache and TLB Updates

One of the biggest changes in the new Sunny Cove core is the cache hierarchy. Throughout most of the last decade, Intel has kept the same cache configuration among its server cores with very few changes, aside from improving the micro-op cache through Sandy Bridge today, but with Sunny Cove, we get some key updates.

From our microarchitecture disclosure article, we know that Sunny Cove brings with it an increased L1 data cache, as well as a doubled L2 cache, from Skylake. With this comes more associativity as well.

Core Cache Comparison
Sunny
Cove
AnandTech Cannon
Lake
Skylake Sandy
Bridge
  AMD
Zen 2
48 KB
12-way
L1-D 32 KB
8-way
32 KB
8-way
32 KB
8-way
  32 KB
8-way
32 KB
8-way
L1-I 32 KB
8-way
32 KB
8-way
32 KB
8-way
  32 KB
8-way
512 KB
8-way
L2 256 KB
4-way
256 KB
4-way
256 KB
8-way
  512 KB
8-way
2 MB
16-way
L3/core 2 MB
16-way
2 MB
16-way
2MB
16-way
  4 MB
16-way
2304 uOp Cache 1536 1536 1536   4096

I’ve also included the size of the micro-op cache in this comparison, because we understand that the L1-I and the micro-op cache are typically located next to each other in the die design – increasing the size of one typically means limiting the size of the other, however given that both of them work to accelerate the same types of data, it is important to find the right balance: AMD for Zen 2 decided to halve the L1-I and double its associativity, and then double the micro-op cache from 2k to 4k entries. For Sunny Cove, Intel has increased the L1-D by 50%, but also increased the micro-op cache by 50%, taking advantage of the second generation 10nm process.

In the above latency graph comparison, we can notably see the new increased cache capacities. The L1’s increase from 32KB to 48KB is well visible, as well as the L2 increase from 256KB to 512KB.

On the part of the L2 it’s interesting to see that again the new core’s TLB structures don’t quite cover the whole capacity of the L2 and that’s why the latter half of the L2 has worse access latencies for L1D TLB miss patterns.

L3 latencies look similar, however we’ll dwell into that just in a bit. The DRAM latencies of course are apples and oranges in this case as Intel’s new LPPDR4X memory controller in the new ICL part doesn’t have a counter-part we can compare to, but as expected the memory latency is notably worse than a desktop part so no big surprises there.

What’s rather disappointing however is that we’re not really seeing any kind of change to the prefetchers and our access patterns between the two microarchitectures look identical. We had expected Intel to improve in this regard, but alas it seems, at least for our test cases, there’s been no improvements.

One of the major balancing acts with cache sizes is also cache latency. The bigger the cache, the longer it takes to retrieve data from it – increasing associativity can do this as well. Intel for the longest time has cited a 4-cycle latency to its L1 cache, and a 12-cycle latency to its L2 cache. This changes, in quite a substantial way.

Core Cache Latency (in cycles)
Sunny Cove AnandTech Cannon
Lake
Skylake Sandy
Bridge
  AMD
Zen 2
5 L1 4 4 4   4
13 L2 12 ~12 12   12
30-36 L3   26-37     34

Due to the increase in the L1 cache, that 4-cycle latency is now a 5-cycle latency. Intel is hoping that its double L1 store bandwidth will help hide that latency, however adding 20% latency onto every data fetch is a heavy hit to take. This is why a lot of the rest of the core is also beefed up, so work can still continue to cover for this extra cycle. It is worth noting that Intel’s Atom cores in the past had an L1 latency of 3 cycles, however they have also since moved to 4-cycle.

The L2 also changes, from 12 cycles to 13 cycles. You can’t double a cache for free, and it is interesting to note here that now AMD and Intel share the same L2 cache size and the same associativity, however AMD has a cycle advantage on Intel. This has a knock on effect for L3 cache latency too, which has increased from ~26-37 cycles to ~30-36 cycles on Intel, from Skylake. The latency here isn’t uniform because the cache isn’t uniform, and accessing non-local L3 slices comes with a latency penalty, as say opposed to AMD’s uniform latency L3.

One of the biggest additions Intel was keen to make in our Sunny Cove microarchitecture disclosure is the increase in the L1 bandwidth. Based on our testing, Skylake’s L1 data cache was capable of 2x32-byte read and 1x32-byte write per clock. For Sunny Cove this has increased, but it gets a bit more complicated. In one clock Sunny cove can perform 2x64-byte reads and either 1x64-byte write, or 1x32-byte write, or 2x16-byte writes. So both reads and writes, at peak, have doubled with bit width, with the write configurations being a bit more complex.

We can see the direct effects of the bandwidth change in our bandwidth tests. The L1 store bandwidth is extremely evident as it measures in at 222GB/s on the ICL part, while only reaching 139GB/s on the 28% higher clocked 9900K. If we normalise for frequency, we indeed see a doubling of the store bandwidth of the new core.

The L2 cache bandwidth looks unchanged from Skylake – the part here lags behind with an equal amount to the frequency difference. Surprisingly, the L3 bandwidth fares quite well here and is almost at parity to the desktop 9900K even though the frequency difference. The DRAM bandwidth is inferior on the ICL mobile chip, but again that’s to be expected due to the apples and oranges DRAM architecture comparison.

Moving on to the TLB configurations, and it turns out that Intel has moved where this data is stored. This data is typically stored in CPUID.02h, however it is now found in CPUID.18h, and the info between different page sizes and capabilities is now given as subdivisions. The TLBs look as follows, and broken down into configurations:

Sunny Cove TLB
AnandTech Type Entries Associativity
L1-D 4K 64 4-way
L1-D 2M 32 4-way
L1-D 1G 8 full
L1-I 4K+2M 8 full
L1-I 4K+2M+1G 16 full
L2 4K+2M 1024 8-way
L2 4K+1G 1024 8-way

This means that for 4K and 2M L1-I entries, there are a total 8+16 = 24 possible, but only 16 1G possible. For 4K L2 entries, there are 1024 + 1024 = 2048 entries possible, however only 1024 each of 2M/1G are possible. The peak numbers align with what Intel has told us in our microarchitecture disclosure, however it is good to dive into what is possible.

Intel 10nm Ice Lake, Sunny Cove, and Gen11 Tested: Details Inside Security Updates, Improved Instruction Performance and AVX-512 Updates
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  • Ratman6161 - Wednesday, August 7, 2019 - link

    "Did we really learn something new from this piece? Not really would be my answer."
    Actually I learned something. To me this showed that once Ice Lake systems hit the market, it will be time for me to start looking for a deal on A Whiskey Lake system. We see potential performance increases in some things but not others and the things more interesting to me personally fall into the tests where there isn't much difference.

    Besides, everyone understands this is a pre-release system and much more data will be needed to really make a decision...at least I thought everyone understands. My personal experience with laptops in general has been that how good the cooling performance is is probably the most important factor in real world performance as most of them will thermal throttle long before you get any kind of sustained performance out of them anyway.
    Reply
  • casperes1996 - Thursday, August 1, 2019 - link

    Don't let comments like this get to you, Ian.

    It was an excellent article, considering the limited time you had with the platform. There will always be people calling fanboyism or the like no matter which company is in focus. You balanced it all as well as you could with the time you had the device for, and it was a great read.
    If anything I'd actually say it sometimes came off as being a bit anti-Intel; Not in terms of their products, but the whole thing with them trying to involve themselves more in how you test their stuff, perhaps to their advantage. Sometimes sounded a bit "Just let me do my job and I'll let you do yours". But I thought that was kinda good ;)
    Reply
  • eva02langley - Friday, August 2, 2019 - link

    Well, the thing is more about the free advertisement. You are not the only one who went there. Toms did and their testing are downright different from yours. I believe your numbers way more than theirs, however there is a cost of being part of scheme like this. Reply
  • CityBlue - Saturday, August 3, 2019 - link

    > We do our own validation of the platform to remove as much Intel involvement as possible.

    You say that, but it's difficult to believe Anandtech can be trusted when you botched the Ryzen 3 benchmark reviews so so badly and have subsequently been in denial ever since (looking at you, Ryan on reddit).

    You personally have suggested that security isn't important so any performance impact resulting from security mitigations doesn't sound like something you would personally care about, thus playing right into the hands of a firm like Intel.

    So, can you trusted? That would be a big fat "no" from me, I'm afraid.
    Reply
  • Jorgp2 - Thursday, August 1, 2019 - link

    Lol, this is exactly what qualcomm does.

    Its just a preview, they will do better testing at release.
    Reply
  • brakdoo - Thursday, August 1, 2019 - link

    Yeah the Qualcomm pieces were problematic too because they could have just released a few benchmarks (and they did) to give us a rough understanding of the performance.

    The real power consumption and performance (especially therm. throttled) came later in real world tests.

    It was not until Andrei compared the 855 to the Kirin 980 when we saw the Kirin to be slightly faster and more efficient in pure CPU tests.

    At least Qualcomm made real statements about release dates and those chips being really high volume. We still don't know whether or not Ice Lake will be in just a few laptops.
    Reply
  • Andrei Frumusanu - Thursday, August 1, 2019 - link

    The 855 preview contained almost our whole test suite, with just the thermal GPU tests missing due to lack of time.

    > It was not until Andrei compared the 855 to the Kirin 980 when we saw the Kirin to be slightly faster and more efficient in pure CPU tests.

    This was included in the preview, and not later:

    https://www.anandtech.com/show/13786/snapdragon-85...

    The S10 review essentially had no changes on those numbers.
    Reply
  • Valantar - Saturday, August 3, 2019 - link

    brakdoo: your stance here is nonsense. You're arguing that it's _more_ problematic to accept special access to do your own independent testing than it is to simply accept a company's marketing statements in good faith? That makes _zero_ sense, and is certainly not how journalism is supposed to work. Articles like this are very valuable as they give interested readers information that can be trusted to a certain degree (even if the test platform isn't what they're going to be buying in the future), unlike marketing statements which always have some spin.

    Ian: Excellent article, and good job getting all that work done in just eight hours. Keep up the good work.
    Reply
  • FunBunny2 - Thursday, August 1, 2019 - link

    "Now 5G is just sub-6 and the only important part is massive MIMO"

    cute. I've been, ever since 5G was a twinkle in the eye of whoever, that mmWave 5G was, and always will be, vaporware. getting it to work in the real world, when engineers and scientists have known for decades how microwave (and near) propagates, is a non-starter. the telecom BS has reached ever new highs.
    Reply
  • Eletriarnation - Thursday, August 1, 2019 - link

    This seems like a good thing to me - we're getting useful information earlier, even if it is limited in scope. It's not like AMD offered the same and you turned them down. Keep up the good work! Reply

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