Following the long gap after the release of PCI Express 3.0 in 2010, the PCI Special Interest Group (PCI-SIG) set about a plan to speed up the development and release of successive PCIe standards. Following this plan, in late 2017 the group released PCIe 4.0, which doubled PCIe 3.0’s bandwidth. Now less than two years after PCIe 4.0 – and with the first hardware for that standard just landing now – the group is back again with the release of the PCIe 5.0 specification, which once again doubles the amount of bandwidth available over a PCI Express link.

Built on top of the PCIe 4.0 standard, the PCIe 5.0 standard is a relatively straightforward extension of 4.0. The latest standard doubles the transfer rate once again, which now reaches 32 GigaTransfers/second. Which, for practical purposes, means PCIe slots can now reach anywhere between ~4GB/sec for a x1 slot up to ~64GB/sec for a x16 slot. For comparison’s sake, 4GB/sec is as much bandwidth as a PCIe 1.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.

The fastest standard on the PCI-SIG roadmap for now, PCIe 5.0’s higher transfer rates will allow vendors to rebalance future designs between total bandwidth and simplicity by working with fewer lanes. High-bandwidth applications will of course go for everything they can get with a full x16 link, while slower hardware such as 40GigE and SSDs can be implemented using fewer lanes. PCIe 5.0’s physical layer is also going to be the cornerstone of other interconnects in the future; in particular, Intel has announced that their upcoming Compute eXpress Link (CXL) cache coherent interconnect will be built on top of PCIe 5.0.

PCI Express Bandwidth
(Full Duplex)
Slot Width PCIe 1.0
(2003)
PCIe 2.0
(2007)
PCIe 3.0
(2010)
PCIe 4.0
(2017)
PCIe 5.0
(2019)
x1 0.25GB/sec 0.5GB/sec ~1GB/sec ~2GB/sec ~4GB/sec
x2 0.5GB/sec 1GB/sec ~2GB/sec ~4GB/sec ~8GB/sec
x4 1GB/sec 2GB/sec ~4GB/sec ~8GB/sec ~16GB/sec
x8 2GB/sec 4GB/sec ~8GB/sec ~16GB/sec ~32GB/sec
x16 4GB/sec 8GB/sec ~16GB/sec ~32GB/sec ~64GB/sec

Meanwhile the big question, of course, is when we can expect to see PCIe 5.0 start showing up in products. The additional complexity of PCIe 5.0’s higher signaling rate aside, even with PCIe 4.0’s protracted development period, we’re only now seeing 4.0 gear start showing up in server products; meanwhile the first consumer gear technically hasn’t started shipping yet. So even with the quick turnaround time on PCIe 5.0 development, I’m not expecting to see 5.0 show up until 2021 at the earliest – and possibly later than that depending on just what that complexity means for hardware costs.

Ultimately, the PCI-SIG’s annual developer conference is taking place in just a few weeks, on June 18th, at which point we should get some better insight as to when the SIG members expect to finish developing and start shipping their first PCIe 5.0 products.

Source: PCI-SIG

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  • ksec - Thursday, May 30, 2019 - link

    PCE-E 4.0 is quite a bit more expensive than 3.0, but you make up the saving by having less lane to reach those bandwidth. I am wondering how much more expensive is it for PCI-E 5.0?

    Now the SSD maker have to figure out a way to make 16GB/s PCI-E 5.0 SSD. :D
    Reply
  • HStewart - Thursday, May 30, 2019 - link

    This could depend on it implemention of PCIe, Just because PCIe 4.0 is more expensive currently, does not mean that PCIe 5.0 will be by another vendor. It just send really fishy that AMD rushes out 4.0 support at very close to time 5.0 spec is out. There must be a reason why Intel skip 4.0. Reply
  • arashi - Thursday, May 30, 2019 - link

    Because 10nm is delayed. Just because Intel hasn't done it (yet) doesn't mean it's problematic.

    HStewart even with the 2 brain cells you have you are aware that PCIe4 support is on Intel's roadmap? Or do I need to deduct another brain cell from your tally?
    Reply
  • ajc9988 - Friday, May 31, 2019 - link

    Intel did NOT skip PCIe 4.0. What you are referring to is their server chips using PCIe 5.0 next year. Moreover, what you are ignoring is CONSUMERS WILL NOT GET PCIe 5.0 ANYTIME SOON!

    In fact, Intel is likely to bring PCIe 4.0 to consumers next year. Then you show your lack of knowledge that implementing it required certain signal integrity parameters in order to implement it. That meant more power on the chipset, that meant higher quality PCBs for motherboards, and for beyond 5-7 inch trace paths, you need signal conditioners/boosters and repeaters to drive beyond that distance. All of this is significant engineering challenges, all of which AMD did with their motherboard partners, whose engineers should be lauded for such achievements to so quickly bring it to mainstream implementations.

    Instead, your trying to crap on AMD is also crapping on those motherboard engineers that worked out the implementation on their end. Good job! /s
    Reply
  • maisonier - Thursday, May 30, 2019 - link

    When are we going to get HBM memory in desktop computers? ... we are still using the crap of DDR and DUAL CHANNEL !!! Reply

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