Today at Computex, AMD CEO Dr. Lisa Su is announcing the raft of processors it will be launching on its new Zen 2 chiplet-based microarchitecture. Among other things, AMD is unveiling its new Ryzen 9 product tier, which it is using for its 12-core Ryzen 9 3900X processor, and which runs at 4.6 GHz boost. All of the five processors will be PCIe 4.0 enabled, and while they are being accompanied by the new X570 chipset launch, they still use the same AM4 socket, meaning some AMD 300 and 400-series motherboards can still be used. We have all the details inside.

A lot of people have been after details about AMD’s next generation Ryzen platform for several months, ever since AMD teased the Matisse Ryzen 3000 design at CES back in January. Most of that information is coming out today, with Ryzen 9, Ryzen 7, and Ryzen 5 processors in the mix. All of these processors will be officially launched on July 7th (which is 7/7), correlating with the fact that the core chiplets of these products are built on TSMC’s 7nm process. This is technically a Sunday, but AMD doesn’t mind too much. In reality, it means users might even get them in the mail on the following Monday.

Before talking about features, let’s go straight into the CPU list, as that’s what most of you are here for.

AMD 'Matisse' Ryzen 3000 Series CPUs
AnandTech Cores
Threads
Base
Freq
Boost
Freq
L2
Cache
L3
Cache
PCIe
4.0
DDR4 TDP Price
(SEP)
Ryzen 9 3900X 12C 24T 3.8 4.6 6 MB 64 MB 16+4+4 ? 105W $499
Ryzen 7 3800X 8C 16T 3.9 4.5 4 MB 32 MB 16+4+4 ? 105W $399
Ryzen 7 3700X 8C 16T 3.6 4.4 4 MB 32 MB 16+4+4 ? 65W $329
Ryzen 5 3600X 6C 12T 3.8 4.4 3 MB 32 MB 16+4+4 ? 95W $249
Ryzen 5 3600 6C 12T 3.6 4.2 3 MB 32 MB 16+4+4 ? 65W $199

The New Flagship: Ryzen 9 3900X

The Ryzen 3000 series will debut a new product tier for AMD: Ryzen 9. In this case, the Ryzen 9 3900X will be AMD’s first mainstream desktop 12-core processor. The processor is the only one of the group that uses two chiplets, in a 6+6 configuration. The 3900X will have a base frequency of 3.8 GHz, a turbo frequency of 4.6 GHz, and line up with 6 MB of L2 cache and 64 MB of L3 cache. This confirms that each chiplet has 32 MB of L3 cache, doubling what we saw on the first generation of the Zen microarchitecture. This CPU has a TDP of 105W, which for AMD processors is usually a good measure of all-core power consumption, and will be enabled with 24 PCIe 4.0 lanes (16 for GPU, 4 for storage, 4 for the chipset).

AMD 'Matisse' Ryzen 3000 Series CPUs
Ryzen 9
AnandTech Cores
Threads
Base
Freq
Boost
Freq
L2
Cache
L3
Cache
PCIe
4.0
DDR4 TDP Price
(SEP)
Ryzen 9 3900X 12C 24T 3.8 4.6 6 MB 64 MB 16+4+4 ? 105W $499

The Ryzen 9 3900X will have a suggested e-tail price of $499, and it will come with a cooler (more details in the coming weeks). AMD compared this processor in its presentations to Intel’s 12-core HEDT processor, the Core i9-9920X, which has an MSRP of $1199 and doesn’t come with a cooler.

In this comparison, AMD provided Cinebench R20 performance data comparing the two processors (it should be noted that we can’t confirm these results at this time). AMD states that in single thread performance, the 3900X beats the 9920X by +14%, and also wins in multi-threaded performance by 6%, all while having a lower TDP (165W vs 105W).

The Ryzen 9 3900X is the new mainstream desktop flagship, although AMD clearly has enough headroom on this design to enable a full 16 cores. Most users will expect this to come in the future, so it will be interesting to see if AMD will strategically play this card.

Mainstream Madness: Ryzen 7 at 65W

For the Ryzen 7 lineup, AMD is keeping this for the 8-core versions. These CPUs only have a single chiplet inside, and no dummy chiplet. Of the two CPUs in this segment, the one that gets a big shock from us is actually the cheaper model.

AMD 'Matisse' Ryzen 3000 Series CPUs
Ryzen 7
AnandTech Cores
Threads
Base
Freq
Boost
Freq
L2
Cache
L3
Cache
PCIe
4.0
DDR4 TDP Price
(SEP)
Ryzen 7 3800X 8C 16T 3.9 4.5 4 MB 32 MB 16+4+4 ? 105W $399
Ryzen 7 3700X 8C 16T 3.6 4.4 4 MB 32 MB 16+4+4 ? 65W $329

The Ryzen 7 3700X is an eight core, sixteen thread CPU with a 3.6 GHz base frequency and a 4.4 GHz turbo frequency. It has 4 MB of L2 and 36 MB of L3 (half the L3 compared to Ryzen 9, because it only has one chiplet), but the amazing thing is that this chip has a TDP of just 65W. Just on paper, it looks like this processor is one of the most efficient x86 performance desktop processors ever made. This is likely the CPU configuration that AMD used in its Cinebench R20 demo back at CES, where it showed R20 equivalent multithreaded performance for 40% less system power. And the price for all this performance? Only $329. If I put my reviewer hat on and look at these specifications at a high level, the Ryzen 7 3700X promises to be the mainstream chip of choice for a substantial number of high-performance PCs this year.

Like with the Ryzen 9 3900X, AMD also ran a Cinebench comparsion with the 8 core Ryzen 3700X versus Intel's mainstream Core i7-9700K. Here they scored 4806, verus 3726 for the 9700K in R20's multithreaded test.

The other CPU in this bracket is the Ryzen 7 3800X. This is going to be the direct upgrade from the current Ryzen 7 2700X, comes with eight cores and sixteen threads, with a base frequency of 3.9 GHz and a boost frequency of 4.5 GHz. It doesn’t seem overly impressive compared to the 3700X with its larger 105W TDP for only a few hundred MHz more on the base frequency, however as we’ve seen with the 2nd Gen Ryzen, that extra TDP headroom usually helps with technologies like XFR that manage the boost frequencies. AMD hasn’t said anything new about how XFR or Precision Boost works in the new generation yet, we have to wait until nearer launch for that information. However the extra frequency and extra TDP will cost an extra $70: the Ryzen 7 3800X will retail for $399.

Budget Builds: Ryzen 5 with Six Cores

Not mentioned during the keynote, but discussed in the press release, AMD also gave information about its new Ryzen 5 processors.

AMD 'Matisse' Ryzen 3000 Series CPUs
Ryzen 5
AnandTech Cores
Threads
Base
Freq
Boost
Freq
L2
Cache
L3
Cache
PCIe
4.0
DDR4 TDP Price
(SEP)
Ryzen 5 3600X 6C 12T 3.8 4.4 3 MB 32 MB 16+4+4 ? 95W $249
Ryzen 5 3600 6C 12T 3.6 4.2 3 MB 32 MB 16+4+4 ? 65W $199

These are still very competitive – users can now buy a six-core processor for under $200. The processor frequencies are commensurate with the position in the stack, along with the pricing, and both CPUs will support all the same technologies (PCIe 4.0, etc) as the bigger chips. These chips still use a single chiplet, not a dual chiplet design.

Performance Numbers

AMD provided some performance numbers to compare AMD to Intel CPUs. All of these tests are using Cinebench R20, which should be noted is a floating point rendering test that AMD already does well on, but there aren’t any specific optimizations here for each CPU.

Direct chip to chip comparisons put AMD’s single thread performance against Intel at +1%. Though it should be noted here that something like the Ryzen 7 3800X, which boosts to 4.5 GHz, is being compared to an Intel CPU that boosts to 5.0 GHz. That would put IPC on this test firmly in the hands of AMD. Multi-threading results are a similar scenario, although the margin of difference tends to drop the more cores that AMD has access to, perhaps because more cores are fighting to get to the memory with a slightly extended memory latency compared from Intel.

Comparing Zen 1 to Zen 2, AMD is promoting that the Ryzen 9 3900X offers +32% better single threaded performance over the Ryzen 7 1800X. Given that we saw a 40-52% IPC increase from pre-Zen to Zen 1, another +32% on single threaded performance is a good amount to have, although that 32% does include frequency uplift. When we get the chips in, we’ll do an obvious comparison test to find the IPC difference. In multi-threaded results, AMD is promoting +100% multithreaded performance, which is helped by +50% more cores, 2x better FP throughput per core, and higher frequencies.

Other Features and X570 Motherboards

Aside from the 7nm chiplets, and the monumental price comparison to Intel, there are some other features to mention. AMD is promoting a +15% direct IPC increase from Zen 1 to Zen 2, due to microarchitecture improvements and cache size doubling on the L3. The CPU has 24 PCIe 4.0 lanes: sixteen for the GPU (or other PCIe cards), four for storage, and four for the chipset. The four for storage will likely be linked to the top M.2 slot. Given that some companies are advertising PCIe 4.0 SSDs here at Computex, we expect more to follow in due course.

The new X570 chipset has 16 lanes, four for the upstream connection to the CPU, and twelve downstream for other devices. There is some discontinuity here – we heard from partners that AMD actually removed four PCIe lanes from the chipset design in order to bring the TDP of the chipset down from 15W to 11W; but the full-fat 15W version will be on the next editions of the high-end desktop (which would suggest that Threadripper isn’t dead, contrary to a lot of reporting – this is a question we will be asking Lisa Su later today). We have already seen a number of X570 motherboards ready to enter the market, and we expect around 25 new X570 models in total. It is clear that motherboard manufacturers are now getting serious on AM4 – some of these boards are likely to retail up to $600. These manufacturers are clearly expecting AMD to hit Intel hard, and have designed the motherboards to match the best that they make for Intel's CPUs.

One bit of information not disclosed is memory support, however given our discussions with AMD’s partners, this is likely to be DDR4-3200 in one module per channel mode. This is a small bump over 2nd Gen Ryzen, but still a welcome one. It will be interesting to see how the memory controller works on this design for pushing that frequency.  The memory frequency and Infinity Fabric frequency are still linked as before, so bumping up the memory frequency has additional benefits.

Finally, the release date for all these CPUs is going to be July 7th. We’re waiting on AMD to disclose the sampling time frame, but our aim is to get our review up on day one. Suggestions for the review are most welcome.

We also have access to Dr. Lisa Su directly after the keynote today, and will write up our Q&A in due course. Stay tuned for that.

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  • AlexByrth - Monday, May 27, 2019 - link

    He was talking about ports from Linux to Windows and vice-versa.
    "Do you know how I know how you know nothing?" : You are the only one talking about consoles here.
    LOL
    Reply
  • peevee - Tuesday, May 28, 2019 - link

    You don't just change the scheduler when changing Linux to Windows. You change the compiler. You change libraries, and both compiler and library options.

    For example, how many porters remember to set their "_SECURE_SCL=0" in Visual Studio options? But without it C++ STL in Visual Studio behaves like Java, checking every access to every container, slowing down some operations by the factor of 20!

    And generally, programming for NUMA is very specific. If all you do is testing on your 4-core desktop/laptop, you will NEVER do it right. OS-specific API usage is a must. And so are NUMA-aware algorithms.

    You change APIs, as, for example, there are no standard APIs for affinities and many other MT issues in standard C/C++ libraries.
    Reply
  • RSAUser - Monday, May 27, 2019 - link

    Shouldn't affect new TR though. Reply
  • Ratman6161 - Tuesday, May 28, 2019 - link

    NPZ. Re-read the first article you quote. You will find this statement:
    "It turns out that Microsoft has a hotfix in place in Windows for dual-NUMA environments ...This is why we see it in quad-die Threadripper and EPYC, and not dual-die Threadripper."

    So this issue wouldn't apply to a ryzen 9 even if it were the full 16 cores.
    Reply
  • Alexvrb - Monday, May 27, 2019 - link

    Another issue is look at the memory topography diagram for a quad-chip Threadripper. Two of the dies aren't connected to RAM directly. That's not an issue for Ryzen 2, latency would be the same with 16 cores as it is with 12. Furthermore I don't think they are running into memory bandwidth issues for most software... outside of iGPUs you don't really need a crapload of bandwidth per core for typical workloads.

    The main reason you see such a benefit with memory clocks and Ryzen is the IF. Adding more cores won't substantially alter IF scaling one way or the other. That's why even 4 and 6 core Ryzen chips benefit so much from high memory clocks, not for the bandwidth but for IF scaling. I suspect that trend will continue with Ryzen 2 based on the article but we will see.
    Reply
  • jamescox - Tuesday, May 28, 2019 - link

    Zen 2 will probably not be anywhere near as sensitive to memory clock as Zen 1. The cpu chiplets do not have any memory clock, so communication between the two CCX on the same die is probably at core clock. Communication between the two chips should also be quite fast due to the much higher IF serdes clock. Also, the IF switch may be in a separate clock domain from the memory controller. Reply
  • peevee - Wednesday, May 29, 2019 - link

    "so communication between the two CCX on the same die is probably at core clock."

    It said in the article that IF still operates on memory clock.
    Reply
  • peevee - Wednesday, May 29, 2019 - link

    "Another issue is look at the memory topography diagram for a quad-chip Threadripper."

    Gimped artificially not to compete with EPYC, as the socket is the same.
    Reply
  • peevee - Wednesday, May 29, 2019 - link

    "That's not an issue for Ryzen 2, latency would be the same with 16 cores as it is with 12. Furthermore I don't think they are running into memory bandwidth issues for most software... outside of iGPUs you don't really need a crapload of bandwidth per core for typical workloads."

    You don't need 16 cores and 32 threads for typical workloads. But for workloads where you DO need them, specifically, where human wait time would be significantly more than on 8 cores, it usually means that amount of data needed to be processed is way more than 64MB of L3 cache, and the data needs to be touched more than once. Say, large codebase compilation. Source files do not fit into 64MB, header files do not into 64MB, object files do not fit, binaries do not fit...
    Real life differs from bad tests which run the same workload over and over again, often disposing few first results etc - like they TRY to make them irrelevant.

    Their 12C upgrade over 8C includes TWICE as much L3 cache. At least something to compensate for increasing data needs of 50% more cores/threads. Probably twice the combined L3 bandwidth as it is on 2 chips now. Now, 16 cores with the SAME amount and bandwidth of L3. 33% more cores but no support for them. Only good for tests.
    Reply
  • stadisticado - Monday, May 27, 2019 - link

    HBM2 is not a reasonable solution on consumer parts. It is too dense and that density makes it too expensive. At cost, a 4GB stack is ~$80. AMD isn't giving it away at cost so assume it adds $150 total to the product. Oh, and then you need to use a silicon interposer because HBM needs a dense connector. That's another $30 that needs to get margined up as well.

    The $500 part they have is now $800 - $900 in order to implement HBM2, that's why they haven't done it, and probably wont.
    Reply

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