2018 was an exciting year for Arm’s own CPU designs. Last year in May we saw the release of the Cortex-A76 and the subsequent resulting silicon in the form of the Kirin 980 as well as Snapdragon 855 SoCs. We were very impressed by the IP, and Arm managed to deliver on all its performance, efficiency and area promises, resulting in some excellent SoCs and devices powering most of 2019’s flagship devices.

This year we follow-up with another TechDay disclosure, and this time around we’re uncovering Arm’s follow-up to the Cortex-A76: the new Cortex-A77. The new generation is a direct evolution of last year’s major microarchitecture introduction, and represents the second instance of Arm’s brand-new Austin core family. Today we’ll analyse how Arm has pushed the IPC of its new microarchitecture and how this will translate into real performance for upcoming late-2019/early-2020 SoCs and devices.

Deimos turns to Cortex-A77

The announcement of the Cortex-A77 doesn’t come as a surprise as Arm continues on their traditional annual IP release cadence. In fact today is not the first time that Arm has talked about the A77: In August of last year Arm had teased the CPU core when releasing its performance roadmap through 2020:

Codenamed as “Deimos”, the new Cortex-A77 picks up where the Cortex-A76 left off and follows Arm’s projected trajectory of delivering a continued solid 20-25% CAGR of performance uplift with each generation of Arm’s new Austin family of CPUs.

Before we dwell into the new Cortex-A77, we should take a look back at how the performance of the A76 has evolved for Arm:

The A76 has certainly been a hugely successful core for Arm and its licensees. The combination of the brand-new microarchitecture alongside the major improvements that the 7nm TSMC process node has brought some of the biggest performance and efficiency jumps we’ve ever seen in the industry.

The results is that the Kirin 980 as well as the Snapdragon 855 both represented major jumps over their predecessors. Qualcomm has proclaimed a 45% leap in CPU performance compared to the previous generation Snapdragon 845 with Cortex-A75 cores, the biggest generational leap ever.

While the performance increase was notable, the energy efficiency gains we saw this generation was even more impressive and directly resulted in improved battery life of devices powered by the new Kirin and Snapdragon SoCS.

While the A76 performed well, we should remember that it does have competition. While Samsung’s own microarchitecture this year with the M4 has lessened the performance/efficiency gap, the Exynos CPU still largely lags behind by a generation, even though this difference is amplified by a process node difference this year (8nm vs 7nm). The real competition for Arm here lies with Apple’s CPU design teams: Currently the A11 and A12 still hold a large performance and efficiency lead that amounts to roughly two microarchitecture generations.


Die shot credit: ChipRebel - Block labelling: AnandTech

One of Arm’s fortes however remains in delivering the best PPA in the industry. Even though the A76’s performance didn’t quite match Apple’s, it managed to achieve outstanding efficiency with incredibly small die area sizes. In fact, this is a conscious design decision by Arm as power efficiency and area efficiency are among the top priorities for Arm’s licensees.

The Cortex-A77: A Top-Level Overview

The Cortex-A77 being a direct microarchitectural successor to the A76 means the new core largely stays in line with the predecessor’s features. Arm states that the core was built in mind with vendors being able to simply upgrade the SoC IP without much effort.

In practice what this means is that the A77 is architecturally aligned with its predecessor, still being an ARMv8.2 CPU core that is meant to be paired with a Cortex-A55 little CPU inside of a DynamIQ Shared Unit (DSU) cluster.

Fundamental configuration features such as the cache sizes of the A77 also haven’t changed compared to its predecessor: We’re still seeing 64KB L1 instruction and data caches, along with a 256 or 512KB L2 cache. It’s interesting here that Arm did design the option for an 1MB L2 cache for the infrastructure Neoverse N1 CPU core (Which itself is derived from the A76 µarch), but chooses to stay with the smaller configuration options on the client (mobile) CPU IP.

As an evolution of the A76, the A77 performance jump as expected won’t be quite as impressive, both from a microarchitecture perspective, but also from an absolute performance standpoint as we’re not expecting large process node improvements for the coming SoC generation.

Here the A77 is projected to still be productised on 7nm process nodes for most customers, and Arm is proclaiming a similar 3GHz peak target frequency as its predecessor. Naturally since frequency isn’t projected to change much, this means that the core’s targeted +20% performance boost can be solely attributed to the IP’s microarchitectural changes.

To achieve the IPC (Instructions per clock) gains, Arm has reworked the microarchitecture and introduced clever new features, generally beefing up the CPU IP to what results in a wider and more performant design.

The Cortex-A77 µarch: Going For A 6-Wide* Front-End
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  • LiverpoolFC5903 - Tuesday, May 28, 2019 - link

    I wonder why do people make these pointless comparisons. You have an OS that doesn't allow you to do half the things you can do on an Android system, so what exactly is the use of a super high powered soc?

    Can you copy music and movies directly into your flash memory?
    Can you attach external memory using OTG?
    Can you use USB OTG peripherals like gamepads and keyboards?
    Can you install apps/software from outside of Apple's closed ecosystem?
    Can you get pointer support in iOS?
    Can you properly manage the files in your smartphone?
    Can your iphone seamlessly interface with your windows PC?
    Reply
  • Phynaz - Thursday, May 30, 2019 - link

    Did you know it’s 2019? 2007 wants their Apple hate back. Reply
  • Valis - Thursday, May 30, 2019 - link

    And 2007 wants its limited OS back. Not to mention the price for 720p devices. Reply
  • Meteor2 - Monday, June 03, 2019 - link

    It's 2019, and iOS is still as restricted as it ever was. Reply
  • jjj - Monday, May 27, 2019 - link

    Will be interesting to see cloud providers adopting the server version. It's small,it's efficient, it's pretty fast, should be good business. Reply
  • Meteor2 - Monday, June 03, 2019 - link

    Server CPUs seem to take a lot longer to reach market; it's still only A72 and A73 stuff at the moment! Much less money for the necessary investment. But when A76 and A77 does reach the server (and maybe the desktop?) it's going to be very exciting. Reply
  • Demaniax - Monday, May 27, 2019 - link

    Can anyone tell me how to learn all of these things ? I mean how does a CPU made. What is a Pipeline ? What is branch prediction ? And all those things. I want to learn everything. But How ? Is there any online course ? Reply
  • frenchy_2001 - Monday, May 27, 2019 - link

    http://lmgtfy.com/?q=cpu+design+class+free+online
    the links to edx and saylor.org would be interesting.
    It all depends on what your background is and how serious you are.
    You can find great resources online, but this is a big and very advanced domain, so you may need to follow intro level classes in digital circuits before being able to follow full architecture.
    Reply
  • suvtab - Tuesday, May 28, 2019 - link

    A book on Computer Architecture (https://en.wikipedia.org/wiki/Computer_architectur... will be a good start point. I personally recommend David Patterson's classical textbook "Computer Architecture: A Quantitative Approach". Reply
  • Santoval - Monday, May 27, 2019 - link

    Quite frankly, moving from a 4-wide to a 6-wide(!) design in the front end doesn't sound as an "evolutionary" design to me. That's an incredibly wide front end, wider even than when the A76 moved from 3-wide to 4-wide. I never expected ARM to go that wide, not so fast anyway. I wonder if the thermals will be affected, while the clocks should normally be lower.
    The addition of a macro-op L0 cache and the reworking of the backend are also quite significant.
    Reply

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