One of the big questions coming out of AMD’s CES announcements was if its new CPU design, codenamed Matisse and which enables two chiplets and an IO die on a single package, would support one of those chiplets being graphics based in order to make an APU. In our discussions with AMD, we received confirmation that this will not be the case.

The new Matisse design is the platform for AMD’s next generation of desktop processors. The layout shown at CES this year represented the design as having a single IO die, about 122.6 mm2 and built on GlobalFoundries 14nm, paired with a chiplet die, about 80.8 mm2, containing eight cores and built on TSMC’s 7nm. There is obviously space on that package for another CPU chiplet, and there has always been questions if the chiplet design is amenable to using a graphics chiplet instead.

AMD stated that, at this time, there will be no version of the current Matisse chiplet layout where one of those chiplets will be graphics. We were told that there will be Zen 2 processors with integrated graphics, presumably coming out much later after the desktop processors, but built in a different design. Ultimately APUs are both mobile first as well as lower cost parts (usually), so different design decisions will have to be made in order to support that market.

This doesn't rule out a future processor using chiplet graphics, this is just for Matisse.

Our contacts at AMD also discussed the TDP range of the upcoming range of Matisse processors. Given AMD’s definition of TDP, relating to the cooling performance required of the CPU cooler, the range of TDPs for Matisse will be the same as current Ryzen 2000-series processors. This means we could see ‘E’ variants as low as 35W TDP, all the way up to the top ‘X’ processors at 105W, similar to the current Ryzen 7 2700X. We were told that the company expects the processors will fit within that range. This should be expected on some level, given the backwards compatibility with current AM4 motherboards on the market with a BIOS update.

Read our announcement on the early preview of the Matisse processors here:

https://www.anandtech.com/show/13829/amd-ryzen-3rd-generation-zen-2-pcie-4-eight-core

 

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  • GreenReaper - Tuesday, April 16, 2019 - link

    You're likely to want the power savings from 7nm on an APU-based laptop - the most practical kind. Reply
  • Teckk - Friday, January 11, 2019 - link

    If they do launch APUs as 3000 series processors it'll add to the confusion 🤔🤦🏻‍♂️ Reply
  • gavbon - Friday, January 11, 2019 - link

    They probably will! Reply
  • edzieba - Friday, January 11, 2019 - link

    3000 series APUs will be Zen+, like the Ryzen 3000 series mobile APUs announced earlier (and same as the 2000 series APUs being one gen behind). APUs using Zen 2 would be 4000 series. Reply
  • Cooe - Friday, January 11, 2019 - link

    Already have. Just like all 14nm Zen Raven Ridge SKUs were under the 2000 series umbrella, all 12nm Zen+ Picasso parts will have 3000 series model numbers (i.e. expect a 3200G & 3400G on desktop). See the just launched 2nd Gen Ryzen Mobile SKUs (using Picasso) for an example. Reply
  • Teckk - Saturday, January 12, 2019 - link

    Cool, thanks for clarifying. Not consistent but that's how they're doing it every time then. 👍 Reply
  • nemi2 - Friday, January 11, 2019 - link

    Please let there be an option for the 2nd chiplet to be a massive amount of level 3/4 cache... Reply
  • PeachNCream - Friday, January 11, 2019 - link

    Cache size increases experience diminished returns so an absurdly large SRAM cache, while admittedly cool on paper, may not justify the cost increase with greater performance. Also the off-die nature of a chiplet being used as a cache pool would likely further reduce cache benefits by adding distance and communication related latency. The nerdy side of me is cheering for HBM, but that Mattise IC package doesn't look like an interposer which, as far as I know, is mandatory for current HBM implementations. That leaves DRAM or some eDRAM/Crystalwell-like animal. DRAM might not like sharing the same IHS and HSF as the rest of the CPU package though it would be a potential competitor for that real estate given the locality of the IO die with its memory controllers. The temperatures DRAM would experience could be detrimental to performance and eDRAM was an Intel thing that offered about 50GB/s which is what DDR4 in dual-channel is now delivering albeit at higher latency. Reply
  • Santoval - Friday, January 11, 2019 - link

    "The nerdy side of me is cheering for HBM, but that Mattise IC package doesn't look like an interposer which, as far as I know, is mandatory for current HBM implementations."
    An interposer is not "mandatory" for HBM. If it was mandatory Kaby Lake-G could not have had its HBM stack connected to the GPU via EMIB. Now, EMIB is quite faster than IF so it would have a bandwidth and latency advantage, at the trade-off of being very close range. Yet I don't see why IF could not be used for HBM.
    Reply
  • Spunjji - Monday, January 14, 2019 - link

    EMIB is an Intel technology, for the time being at least. I very much doubt we'll see it on an AMD CPU any time soon. Reply

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