It has been hard to miss the fact that Intel has been vacuuming up a lot of industry talent, which brings with them a lot of experience. Renduchintala, Koduri, Keller, Hook, and Carvill, are just to name a few. This new crew has decided to break Intel out of its shell for the first time in a while, holding the first in a new tradition of Intel Architecture Days. Through the five hours of presentations, Intel lifted the lid on the CPU core roadmaps through 2021, the next generation of integrated graphics, the future of Intel’s graphics business, new chips built on 3D packaging technologies, and even parts of the microarchitecture for the 2019 consumer processors. In other words, it's many of the things we've been missing out on for years. And now that Intel is once again holding these kinds of disclosures, there’s a lot to dig in to.

Contents List

Intel covered a good amount of ground at the Architecture Day, which we’ve split into the following categories:

  1. The CPU Core and Atom Roadmaps, on 10nm
  2. The Sunny Cove Microarchitecture
  3. The Next Generation Gen11 Graphics
  4. Intel Demonstrates Sunny Cove and Gen11 Graphics
  5. Beyond Gen11 Graphics: Announcing the Xe Graphics Brand
  6. 3D Packaging with FOVEROS
  7. Intel’s first Fovoros and first Hybrid x86 CPU: Core plus Atom in 7 W on 10nm
  8. Ice Lake 10nm Xeon
  9. Intel Made Something Really Funny: Q&A with Raja, Jim, and Murthy

 

The CPU Core Roadmaps

It is common for companies like Intel to ask members of the press what they enjoy about announcements from Intel, Intel’s competitors, or other companies in the industry. One of answers I will never tire of saying is ‘roadmaps’. The roadmap is a simple document but it enables a company to explain part of its future plans in a very easy to understand way. It shows to the press, to customers, and to partners, that the company has a vision beyond the next product and that it expects to deliver at a rough cadence, hopefully with some markers on expected performance additions or improvements. Roadmaps are rarely taken as set in stone either, with most people understanding that they have an element of fuzziness depending on external factors.

To that end, I’ve been requesting Intel to show roadmaps for years. They used to be common place, but ever since Skylake, it has kind of dried up. In recent months Intel has shown rough datacentre roadmaps, with Cascade Lake, Cooper Lake, and Ice Lake and the next few generations. But for the Core family it has been somewhat more difficult. Depending on which analyst you talk to, a good number will point to some of the Skylake derivatives as being holding points while the issues with 10nm have been sorted out. But nonetheless, all we tend to hear about is the faint whisper of a codename potentially, which doesn’t mean much.

So imagine my delight when we get not one roadmap from Intel on CPUs, but two. Intel gave us both the Core architecture roadmap and the Atom architecture roadmap for the next few generations.

For the high performance Core architecture, Intel lists three new codenames over the next three years. To be very clear here, these are the codenames for the individual core microarchitecture, not the chip, which is an important departure from how Intel has previously done things.

Sunny Cove, built on 10nm, will come to market in 2019 and offer increased single-threaded performance, new instructions, and ‘improved scalability’. Intel went into more detail about the Sunny Cove microarchitecture, which is in the next part of this article. To avoid doubt, Sunny Cove will have AVX-512. We believe that these cores, when paired with Gen11 graphics, will be called Ice Lake.

Willow Cove looks like it will be a 2020 core design, most likely also on 10nm. Intel lists the highlights here as a cache redesign (which might mean L1/L2 adjustments), new transistor optimizations (manufacturing based), and additional security features, likely referring to further enhancements from new classes of side-channel attacks.

Golden Cove rounds out the trio, and is firmly in that 2021 segment in the graph. Process node here is a question mark, but we’re likely to see it on 10nm and or 7nm. Golden Cove is where Intel adds another slice of the serious pie onto its plate, with an increase in single threaded performance, a focus on AI performance, and potential networking and AI additions to the core design. Security features also look like they get a boost.

Intel Core Microarchitecture Roadmap
Core Name Year Process Node Improvements
Skylake 2015 14 nm Single Threaded Performance
Lower Power
Other Optimizations
Kaby Lake 2016 14 nm+ Frequency
Coffee Lake 2017 14 nm++ Frequency
Coffee Refresh 2018 14 nm++ Frequency
Sunny Cove 2019 10 nm Single Threaded Performance
New Instructions
Improved Scalability
Willow Cove 2020 ? 10 nm ? Cache Redesign
New Transistor Optimization
Security Features
Golden Cove 2021 ? 7 / 10 nm ? Single Threaded Performance
AI Performance
Networking / 5G Performance
Security Features

The lower-powered Atom microarchitecture roadmap is on a slower cadence than the Core microarchitecture, which is not surprising given its history. Seeing as how Atom has to fit into a range of devices, we’re expecting there to be a wide range in capabilities, especially from the SoC side.

The upcoming microarchitecture for 2019 is called Tremont, which focuses on single threaded performance increases, battery life increases, and network server performance. Based on some of the designs later in this article, we think that this will be a 10nm design.

Following Tremont will be Gracemont, which Intel lists as a 2021 product. As Atom is designed to continually push both the performance at the high-end of its capabilities and the efficiency at the low-end, Intel lists that Gracemont will have additional single threaded performance and a focus on increased frequency. This will be combined with additional vector performance, which likely means that Atom will get some wider vector units or support new vector instructions.

Beyond this will be a future ‘mont’ core (and not month as listed in the image). Here Intel is spitballing what this new 2023 core might have, for which the general listing of performance, frequency and features is there.

Intel Atom Microarchitecture Roadmap
  Year Process Improvements
Goldmont 2016 14 nm Higher Performance
Cryptography Features
Goldmont Plus 2017 14 nm Branch Prediction
More Execution
Larger Load/Store Buffers
More Cache
- 2018 - -
Tremont 2019 10 nm ? Single Threaded Performance
Network Server Performance
Battery Life
- 2020 - -
Gracemont 2021 10 nm ? Single Threaded Performance
Frequency
Vector Performance
- 2022 - -
'Next Mont' 2023 ? Single Threaded Performance
Frequency
'Features'

As stated above, these are just the microarchitecture names. The actual chips these cores are in will likely have different names, which means a Lake name for the Core microarchitecture. At the event, Intel stated that Ice Lake would have Sunny Cove cores in it, for example.

Another aspect to Intel’s presentations was that future microarchitectures are likely to be uncoupled from any process technologies. In order to build some resiliency into the company’s product line moving forward, both Raja Koduri and Dr. Murthy Renduchintala explained that future microarchitectures will not be process dependent, and the latest products will come to market on the best process technologies available at the time. As a result we’re likely to see some of the Core designs straddle different manufacturing technologies.

Intel also went into a bit of detail on microarchitecture of Sunny Cove.

Sunny Cove Microarchitecture: A Peek At the Back End
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  • f1nalpr1m3 - Wednesday, December 12, 2018 - link

    Yeah, they totally put it together in three weeks and everything.

    Get a clue.
    Reply
  • pkgtech - Thursday, December 20, 2018 - link

    For years Sohail Ahmed was the roadblock to Intel doing any creative package technology by blocking silicon support. He finally was shown for what he was after 2+ year process technology delays and re-invented this. Good riddance Sohail Reply
  • Adonisds - Wednesday, December 12, 2018 - link

    How do the Intel process delays influence their microarchitecture plans? 10 nm was already supposed to be here and with it its new microarchitecture, Ice Lake. Does the Ice Lake design continue to get improved as the delays kept happening or was it finalized years ago? Why? What about the microarchutectures succeeding Ice Lake? Reply
  • III-V - Wednesday, December 12, 2018 - link

    This is Ice Lake. Might be a 14nm port (unclear at this point why the name change), but it's at the very least a close relative. Reply
  • III-V - Wednesday, December 12, 2018 - link

    Actually, given the name on the heat sink, it is probably just straight up Ice Lake Reply
  • HStewart - Thursday, December 13, 2018 - link

    I believe the road map states Ice Lake will be on 10nm. More importantly it will be on Sunny Cove which is significant update to Architexture. Reply
  • AdhesiveTeflon - Wednesday, December 12, 2018 - link

    Intel and their naming scheme....they should call one "blue slushie lake" Reply
  • prisonerX - Wednesday, December 12, 2018 - link

    Plans? Intel are in full scale panic mode right now. I'm sure they have new plans every week. Reply
  • jjj - Wednesday, December 12, 2018 - link

    LOL you went in full fanboy mode with the 144mm package being small.
    The package is that size for PoP, the die is much much smaller, they can fit way more 10nm cores than that in such a large area, even without a base die.
    Anyway, there are no relevant details on Foveros and that's problematic. The first question is cost, then you would want to know details about pitch and so on. Intel is by no means the first to announce such a solution so the details are what matters.
    This is how you get to a 3D monolithic die in some years so any foundry that wants to stay in the most advanced node game, needs to push the packaging roadmap.
    Reply
  • Ian Cutress - Wednesday, December 12, 2018 - link

    I specifically said the package was small, and the die was smaller than the package. Reply

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