The A12 Vortex CPU µarch

When talking about the Vortex microarchitecture, we first need to talk about exactly what kind of frequencies we’re seeing on Apple’s new SoC. Over the last few generations Apple has been steadily raising frequencies of its big cores, all while also raising the microarchitecture’s IPC. I did a quick test of the frequency behaviour of the A12 versus the A11, and came up with the following table:

Maximum Frequency vs Loaded Threads
Per-Core Maximum MHz
Apple A11 1 2 3 4 5 6
Big 1 2380 2325 2083 2083 2083 2083
Big 2   2325 2083 2083 2083 2083
Little 1     1694 1587 1587 1587
Little 2       1587 1587 1587
Little 3         1587 1587
Little 4           1587
Apple A12 1 2 3 4 5 6
Big 1 2500 2380 2380 2380 2380 2380
Big 2   2380 2380 2380 2380 2380
Little 1     1587 1562 1562 1538
Little 2       1562 1562 1538
Little 3         1562 1538
Little 4           1538

Both the A11 and A12’s maximum frequency is actually a single-thread boost clock – 2380MHz for the A11’s Monsoon cores and 2500MHz for the new Vortex cores in the A12. This is just a 5% boost in frequency in ST applications. When adding a second big thread, both the A11 and A12 clock down to respectively 2325 and 2380MHz. It’s when we are also concurrently running threads onto the small cores that things between the two SoCs diverge: while the A11 further clocks down to 2083MHz, the A12 retains the same 2380 until it hits thermal limits and eventually throttles down.

On the small core side of things, the new Tempest cores are actually clocked more conservatively compared to the Mistral predecessors. When the system just had one small core running on the A11, this would boost up to 1694MHz. This behaviour is now gone on the A12, and the clock maximum clock is 1587MHz. The frequency further slightly reduces to down to 1538MHz when there’s four small cores fully loaded.

Much improved memory latency

As mentioned in the previous page, it’s evident that Apple has put a significant amount of work into the cache hierarchy as well as memory subsystem of the A12. Going back to a linear latency graph, we see the following behaviours for full random latencies, for both big and small cores:

The Vortex cores have only a 5% boost in frequency over the Monsoon cores, yet the absolute L2 memory latency has improved by 29% from ~11.5ns down to ~8.8ns. Meaning the new Vortex cores’ L2 cache now completes its operations in a significantly fewer number of cycles. On the Tempest side, the L2 cycle latency seems to have remained the same, but again there’s been a large change in terms of the L2 partitioning and power management, allowing access to a larger chunk of the physical L2.

I only had the test depth test up until 64MB and it’s evident that the latency curves don’t flatten out yet in this data set, but it’s visible that latency to DRAM has seen some improvements. The larger difference of the DRAM access of the Tempest cores could be explained by a raising of the maximum memory controller DVFS frequency when just small cores are active – their performance will look better when there’s also a big thread on the big cores running.

The system cache of the A12 has seen some dramatic changes in its behaviour. While bandwidth is this part of the cache hierarchy has seen a reduction compared to the A11, the latency has been much improved. One significant effect here which can be either attributed to the L2 prefetcher, or what I also see a possibility, prefetchers on the system cache side: The latency performance as well as the amount of streaming prefetchers has gone up.

Instruction throughput and latency

Backend Execution Throughput and Latency
  Cortex-A75 Cortex-A76 Exynos-M3 Monsoon | Vortex
  Exec Lat Exec Lat Exec Lat Exec Lat
Integer Arithmetic
ADD
2 1 3 1 4 1 6 1
Integer Multiply 32b
MUL
1 3 1 2 2 3 2 4
Integer Multiply 64b
MUL
1 3 1 2 1
(2x 0.5)
4 2 4
Integer Division 32b
SDIV
0.25 12 0.2 < 12 1/12 - 1 < 12 0.2 10 | 8
Integer Division 64b
SDIV
0.25 12 0.2 < 12 1/21 - 1 < 21 0.2 10 | 8
Move
MOV
2 1 3 1 3 1 3 1
Shift ops
LSL
2 1 3 1 3 1 6 1
Load instructions 2 4 2 4 2 4 2  
Store instructions 2 1 2 1 1 1 2  
FP Arithmetic
FADD
2 3 2 2 3 2 3 3
FP Multiply
FMUL
2 3 2 3 3 4 3 4
Multiply Accumulate
MLA
2 5 2 4 3 4 3 4
FP Division (S-form) 0.2-0.33 6-10 0.66 7 >0.16 12 0.5 | 1 10 | 8
FP Load 2 5 2 5 2 5    
FP Store 2 1-N 2 2 2 1    
Vector Arithmetic 2 3 2 2 3 1 3 2
Vector Multiply 1 4 1 4 1 3 3 3
Vector Multiply Accumulate 1 4 1 4 1 3 3 3
Vector FP Arithmetic 2 3 2 2 3 2 3 3
Vector FP Multiply 2 3 2 3 1 3 3 4
Vector Chained MAC
(VMLA)
2 6 2 5 3 5 3 3
Vector FP Fused MAC
(VFMA)
2 5 2 4 3 4 3 3

To compare the backend characteristics of Vortex, we’ve tested the instruction throughput. The backend performance is determined by the amount of execution units and the latency is dictated by the quality of their design.

The Vortex core looks pretty much the same as the predecessor Monsoon (A11) – with the exception that we’re seemingly looking at new division units, as the execution latency has seen a shaving of 2 cycles both on the integer and FP side. On the FP side the division throughput has seen a doubling.

Monsoon (A11) was a major microarchitectural update in terms of the mid-core and backend. It’s there that Apple had shifted the microarchitecture in Hurricane (A10) from a 6-wide decode from  to a 7-wide decode. The most significant change in the backend here was the addition of two integer ALU units, upping them from 4 to 6 units.

Monsoon (A11) and Vortex (A12) are extremely wide machines – with 6 integer execution pipelines among which two are complex units, two load/store units, two branch ports, and three FP/vector pipelines this gives an estimated 13 execution ports, far wider than Arm’s upcoming Cortex A76 and also wider than Samsung’s M3. In fact, assuming we're not looking at an atypical shared port situation, Apple’s microarchitecture seems to far surpass anything else in terms of width, including desktop CPUs.

The Apple A12 - First Commercial 7nm Silicon SPEC2006 Performance: Reaching Desktop Levels
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  • phoenix_rizzen - Friday, October 05, 2018 - link

    You mean Qualcomm, not 3Com. :) Reply
  • bull2760 - Sunday, October 07, 2018 - link

    Yes thank you sorry meant Qualcomm, my bad. Reply
  • varase - Friday, October 05, 2018 - link

    I just downloaded 12.1 Developer Beta 2 and in my 2 bar AT&T household, I went up from about 11 mbps to 38 mbps.

    My local cell tower probably doesn't have 4x4 mimo, though my Orbis are pushing 298 mpbs through wifi and saturating my internet link.

    It's a little early to jump ship - there's bound to be a few rough edges that'll have to get filed down :-).
    Reply
  • Speedfriend - Monday, October 08, 2018 - link

    What, your mobile data speed has been only 11mbps, where do you live? How on earth do you use your phone like that! I regularly get over 100mbps where I live in London, with the highest I have recorded being 134mbps Reply
  • bull2760 - Sunday, October 14, 2018 - link

    Little early to jump ship. Do you remember antennagate? Steve Jobs answer to a design issue, “you are holding the phone wrong”. Sorry not forming out 1500 for a phone that has cellular as well as network related issues. How this ever passed inspection in testing is beyond me. I’m an Apple fan, have owned every iPhone since they started making them. This is without a doubt the worst performing iPhone I ever purchased. Yes it was snappy and apps flew open. But if I can’t use the phone aspect or wireless networking at home, I may as well hold a paperweight to my ear. I’m heavily entrenched into the Apple ecosystem. Watches, TV, iPads and MacBook Pro. Not to mention all the movies, music and apps that I’ve purchased. This pisses me off. 1500 for a piece a shit phone that was not properly tested before being released. Reply
  • Marlin1975 - Friday, October 05, 2018 - link

    The thing that jumps out to me is the power usage and performance gains at the same time. TSMC's 7nm process looks really good. I wonder if this will also play out on CPUs/GPUs on the same process coming soon. Reply
  • melgross - Saturday, October 06, 2018 - link

    It’s hard to say how much of what Apple gets out of these processes others will get. Apple has bought a lot of equipment for TSMC, as they’ve done for other companies, including Samsung, over the years. What they get out of it is early access to new processes, as well as some more specialized features that they have often developed themselves, as well as extra discounts. Reply
  • KPOM - Friday, October 05, 2018 - link

    Intel should be worried. Reply
  • varase - Friday, October 05, 2018 - link

    I still think the star of the show may end up being the neural processor, up from 660 billion ops/sec to 5 trillion (9x the speed at a tenth the energy usage) - now available to developers via Core ML 2, and now pipelined through the ISP. Reply
  • NICOXIS - Friday, October 05, 2018 - link

    I wonder how A12 would do on Android or Windows... I'm not into Apple but they have done a fantastic job with their SoC Reply

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