SPEC2006 Performance: Reaching Desktop Levels

It’s been a while now since we attempted SPEC on an iOS device – for various reasons we weren’t able to continue with that over the last few years. I know a lot of people were looking forward to us picking back up from where we left, and I’m happy to share that I’ve spent some time getting a full SPEC2006 harness back to work.

SPEC2006 is an important industry standard benchmark and differentiates itself from other workloads in that the datasets that it works on are significantly larger and more complex. While GeekBench 4 has established itself as a popular benchmark in the industry – and I do praise on the efforts on having a full cross-platform benchmark – one does have to take into account that it’s still relatively on the light side in terms of program sizes and the data sizes of its workloads. As such, SPEC2006 is much better as a representative benchmark that fully exhibits more details of a given microarchitecture, especially in regards to the memory subsystem performance.

The following SPEC figures are declared as estimates, as they were not submitted and officially validated by SPEC. The benchmark libraries were compiled with the following settings:

  • Android: Toolchain: NDK r16 LLVM compiler, Flags: -Ofast, -mcpu=cortex-A53
  • iOS: Toolchain: Xcode 10, Flags: -Ofast

On iOS, 429.mcf was a problem case as the kernel memory allocator generally refuses to allocate the single large 1.8GB chunk that the program requires (even on the new 4GB iPhones). I’ve modified the benchmark to use only half the amount of arcs, thus roughly reducing the memory footprint to ~1GB. The reduction in runtime has been measured on several platforms and I’ve applied a similar scaling factor to the iOS score – which I estimate to being +-5% accurate. The remaining workloads were manually verified and validated for correct execution.

The performance measurement was run in a synthetic environment (read: bench fan cooling the phones) where we assured thermals wouldn’t be an issue for the 1-2 hours it takes to complete a full suite run.

In terms of data presentation, I’m following of earlier articles this year such as the Snapdragon 845 and Exynos 9810 evaluation in our Galaxy S9 review.

When measuring performance and efficiency, it’s important to take three metrics into account: Evidently, the performance and runtime of a benchmark, which in the graphs below is represented on the right axis, growing from the right. Here the bigger the figures, the more performant a SoC/CPU has benchmarked. The labels represent the SPECspeed scores.

On the left axis, the bars are representing the energy usage for the given workload. The bars grow from the left, and a longer bar means more energy used by the platform. A platform is more energy efficient when the bars are shorter, meaning less energy used. The labels showcase the average power used in Watts, which is still an important secondary metric to take into account in thermally constrained devices, as well as the total energy used in Joules, which is the primary efficiency metric.

The data is ordered as in the legend, and colour coded by different SoC vendor as well as shaded by the different generations. I’ve kept the data to the Apple A12, A11, Exynos 9810 (at 2.7 and 2.3GHz), Exynos 8895, Snapdragon 845 and Snapdragon 835. This gives us an overview of all relevant CPU microarchitectures over the last two years.

Starting off with the SPECint2006 workloads:

The A12 clocks in at 5% higher than the A11 in most workloads, however we have to keep in mind we can’t really lock the frequencies on iOS devices, so this is just an assumption of the runtime clocks during the benchmarks. In SPECint2006, the A12 performed an average of 24% better than the A11.

The smallest increases are seen in 456.hmmer and 464.h264ref – both of these tests are the two most execution bottlenecked tests in the suite. As the A12 seemingly did not really have any major changes in this regard, the small increase can be mainly attributed to the higher frequency as well as the improvements in the cache hierarchy.

The improvements in 445.gobmk are quite large at 27% - the characteristics of the workload here are bottlenecks in the store address events as well as branch mispredictions. I did measure that the A12 had some major change in the way stores across cache lines were handled, as I’m not seeing significant changes in the branch predictor accuracy.

403.gcc partly, and most valid for 429.mcf, 471.omnetpp, 473.Astar and 483.xalancbmk are sensible to the memory subsystem and this is where the A12 just has astounding performance gains from 30 to 42%. It’s clear that the new cache hierarchy and memory subsystem has greatly paid off here as Apple was able to pull off one of the most major performance jumps in recent generations.

When looking at power efficiency – overall the A12 has improved by 12% - but we have to remember that we’re talking about 12% less energy at peak performance. The A12 showcasing 24% better performance means were comparing two very different points at the performance/power curve of the two SoCs.

In the benchmarks where the performance gains were the largest – the aforementioned memory limited workloads – we saw power consumption rise quite significantly. So even though 7nm promised power gains, Apple's opted to spend more energy than what the new process node has saved, so average power across the totality of SPECint2006 did go up from ~3.36W on the A11 to 3.64W on the A12.

Moving on to SPECfp2006, we are looking at the C and C++ benchmarks, as we have no Fortran compiler in XCode, and it is incredibly complicated to get one working for Android as it’s not part of the NDK, which has a deprecated version of GCC.

SPECfp2006 has a lot more tests that are very memory intensive – out of the 7 tests, only 444.namd, 447.dealII, and 453.povray don’t see major performance regressions if the memory subsystem isn’t up to par.

Of course this majorly favours the A12, as the average gain for SPECfp is 28%. 433.milc here absolutely stands out with a massive 75% gain in performance. The benchmark is characterised by being instruction store limited – again part of the Vortex µarch that I saw a great improvement in. The same analysis applies to 450.soplex – a combination of the superior cache hierarchy and memory store performance greatly improves the perf by 42%.

470.lbm is an interesting workload for the Apple CPUs as they showcase multi-factor performance advantages over competing Arm and Samsung cores. Qualcomm’s Snapdragon 820 Kryo CPU oddly enough still outperforms the recent Android SoCs. 470.lbm is characterised by extremely large loops in the hottest piece of code. Microarchitectures can optimise such workloads by having (larger) instruction loop buffers, where on a loop iteration the core would bypass the decode stages and fetch the instructions from the buffer. It seems that Apple’s microarchitecture has some kind of such a mechanism. The other explanation is also the vector execution performance of the Apple cores – lbm’s hot loop makes heavy use of SIMD, and Apple’s 3x execution throughput advantage is also likely a heavy contributor to the performance.

Similar to SPECint, the SPECfp workload which saw the biggest performance jumps also saw an increase in their power consumption. 433.milc saw an increase from 2.7W to 4.2W, again with a 75% performance increase.

Overall the power consumption has seen a jump from 3.65W up to 4.27W. The overall energy efficiency has increased in all tests but 482.sphinx3, where the power increase hit the maximum across all SPEC workloads for the A12 at 5.35W. The total energy used for SPECfp2006 for the A12 is 10% lower than the A11.

I didn’t have time to go back and measure the power for the A10 and A9, but generally they’re in line around 3W for SPEC. I did run the performance benchmarks, and here’s an aggregate performance overview of the A9 through to the A12 along with the most recent Android SoCs, for those who are looking into comparing past Apple generations.

Overall the new A12 Vortex cores and the architectural improvements on the SoC’s memory subsystem give Apple’s new piece of silicon a much higher performance advantage than Apple’s marketing materials promote. The contrast to the best Android SoCs have to offer is extremely stark – both in terms of performance as well as in power efficiency. Apple’s SoCs have better energy efficiency than all recent Android SoCs while having a nearly 2x performance advantage. I wouldn’t be surprised that if we were to normalise for energy used, Apple would have a 3x performance lead.

This also gives us a great piece of context for Samsung’s M3 core, which was released this year: the argument that higher power consumption brings higher performance only makes sense when the total energy is kept within check. Here the Exynos 9810 uses twice the energy over last year’s A11 – at a 55% performance deficit.

Meanwhile Arm’s Cortex A76 is scheduled to arrive inside the Kirin 980 as part of the Huawei Mate 20 in just a couple of weeks – and I’ll be making sure we’re giving the new flagship a proper examination and placing among current SoCs in our performance and efficiency graph.

What is quite astonishing, is just how close Apple’s A11 and A12 are to current desktop CPUs. I haven’t had the opportunity to run things in a more comparable manner, but taking our server editor, Johan De Gelas’ recent figures from earlier this summer, we see that the A12 outperforms a moderately-clocked Skylake CPU in single-threaded performance. Of course there’s compiler considerations and various frequency concerns to take into account, but still we’re now talking about very small margins until Apple’s mobile SoCs outperform the fastest desktop CPUs in terms of ST performance. It will be interesting to get more accurate figures on this topic later on in the coming months.

The A12 Vortex CPU µarch: Massive Memory Improvements The A12 Tempest CPU & NN Performance Tests
Comments Locked

253 Comments

View All Comments

  • peevee - Monday, October 15, 2018 - link

    "we see four new smaller efficiency cores named “Mistral”. The new small cores bring some performance improvements, but it’s mostly in terms on power and power efficiency where we see Tempest make some bigger leaps"

    So, is it Tempest or Mistral? Or both?
  • Ryan Smith - Tuesday, October 23, 2018 - link

    It's Tempest. Thanks for the heads up!
  • peevee - Monday, October 15, 2018 - link

    "upgrade in sensor size from an area of 32.8mm² to 40.6mm²"

    These are not sensor sizes, these are total image chip sizes.
    Sensor (as in "sensor", the part which actually "senses" light) sizes are not hard to calculate, and are MUCH smaller.

    12MP is approx 4000x3000 pixels.
    The old sensor had 1.22 µm pixel pitch. 1.22*4=4.88mm. 1.22*3=3.66mm.
    So old sensor was 4.88x3.66mm = 17.9mm².

    The new sensor is 5.6mm x 4.2mm = 23.5mm².

    This is is comparison to

    - typical cheap P&S camera sensor size (so-called '1/2.3" type') of 6mm x 4.5mm = 27mm²
    - high-end P&S camera sensor, (1" type) of 13.2mm x 8.8mm = 116mm²
    - Four Thirds camera sensor size of 17.2 x 13mm = 225mm²
    - Modern pro camera sensor size of about 36x24mm = 864mm².

    Please do not confuse your readers by calling total image chip sizes as "sensor size".
  • peevee - Monday, October 15, 2018 - link

    "The performance measurement was run in a synthetic environment (read: bench fan cooling the phones) where we assured thermals wouldn’t be an issue for the 1-2 hours it takes to complete a full suite run."

    Which makes the whole thing useless. Of course wider (read hotter and less efficient due to higher overhead of often-useless blocks) will run faster in this environment, unlike in user hands (literally, ~36C/97F plus blanketing effect).
  • Andrei Frumusanu - Monday, October 22, 2018 - link

    It changes absolutely nothing. It will still reach that performance even in your hands. The duration of a workload is not orthogonal to its complexity.
  • viczy - Sunday, October 21, 2018 - link

    Fantastic and in-depth work! Thanks for the data and analysis. I would like to know a little more about your method for energy and power measurement. Thanks!
  • techbug - Friday, November 2, 2018 - link

    Thanks a lot Andrei.

    L2 cache latency is 8.8ns, Core clock speed is 2.5GHz, each cycle is around 0.4ns, then the l2 cache latency is 8.8ns/0.4=22 cycles. This is much longer than Skylake, which is around 12 cycles (taking i7-6700 Skylake 4.0 GHz at https://www.7-cpu.com/cpu/Skylake.html as an example, it equals to 3ns L2 cache latency).

    So L2 latency is 8.8ns versus 3ns in skylake. Is this comparison correct?

    I cannot tell the precise L1 latency from the graph "Much improved memory latency". Can you give the number?
    According to Figure 3 in https://www.spec.org/cpu2006/publications/SIGARCH-... the working set size of 80% SPEC2K6 workload is larger than 8MB, A12 's L2 cache (8MB) won't hold the working set. Compared with 32MB L3 cache Skylake configuration.

    So overall the memory hierarchy of A12 seems not comparable to Skylake. What else helps it to deliver a comparable SPEC2K6 performance?
  • demol3 - Wednesday, December 5, 2018 - link

    Will there be a comparison between XS-series and XR or XR review anytime soon?
  • tfouto - Thursday, December 27, 2018 - link

    Does XS has a true 10-bit panel, or uses Frame Rate Control?
    What about Iphone X?
  • Latiosxy - Wednesday, January 23, 2019 - link

    Hello. I just wanted to criticize the way this site works. It’s hard to read while listening to music when your intrusive ads follow my screen and interrupt my audio consistently. Please fix this as this has been really annoying. Thanks.

Log in

Don't have an account? Sign up now