Making the Most of Memory: Optane DC Persistent Memory

The week before Computex, Intel announced its new Optane DIMMs, and stated that they will be coming to market in three capacities: 128GB, 256GB, and 512GB. The new persistent memory was explained as being a high capacity SSD with that acts as DRAM with similar latencies, available to hold large databases or enable systems to quickly recover from power loss to improve uptimes.

The Hot Chips presentation confirms that the new Optane DIMMs will be enabled at one per memory channel, allowing a single socket to contain six memory modules and six Optane DIMMs at once. For those counting along at home, that is a 128 GB LRDIMM + 512 GB of Optane per channel, or 3840GB per socket.

What this doesn’t state is if Optane will be supported on all processors, or select high-memory SKUs at extra cost. We have seen a few prices flying around for the 512 GB DIMMs, although we cannot verify this. Intel’s own @IntelBusiness Twitter account recently posted this picture, attempting to show that the DIMMs were shipping.

I’m pretty sure the people on the left are making the money hand gesture

If Intel is shipping Optane DIMMs in this quantity already, that means that high-profile customers that are part of Intel’s Early Sampling program are already buying them in bulk quantities. It will be interesting to see if they ever post any data about the product.

Unanswered Questions

Sure, it is frustrating that Intel has not opened the lid fully on Cascade Lake yet. The pure takeaway I can give you is that I suspect the processors will be optimized for efficiency and frequencies will improve, but the core designs will likely look very much the same as we have now. Intel will be using the opportunity, alongside the DIMMs and VNNI, to offer a product that has a number of the Spectre and Meltdown variants fixed in hardware. A lot of people are waiting for these parts, and are prepared to pay for them. It will be interesting to see what the pricing will be later in the year.

Slide Deck

Related Reading

Process Tuning and VNNI
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  • HStewart - Monday, August 20, 2018 - link

    It very possibility that Variant 1 is not volubility in the hardware designed but how OS developers use the code. Reply
  • GreenReaper - Monday, August 20, 2018 - link

    Well, it's a problem for all software with secrets it wants to keep, and means of speculation involving access to them. The most common example of this is the OS/VMM.

    The core issue is that the speed of access to data is non-deterministic in the x86 model. Nothing in the original design said "you can't *try* to go faster than you would if you had to load everything only at the point that it came up" - indeed, doing so has been viewed as a feature for decades.

    Meanwhile timing attacks have been viewed as relatively hard to exploit. But there are many ways in which a timing gadget may be constructed, this is arguably just a newly-discovered pattern commonly used by privileged software.
    Reply
  • HStewart - Monday, August 20, 2018 - link

    Unfortunately today we have increase of hackers that will try to take advantage of such features to hamper system. Which cause headaches for both CPU designers and OS designers.

    Also the following link as interesting statement about these attacks not being just Intel.

    It actually states "This contradicts some early statements made about the Meltdown vulnerability as being Intel-only"

    https://en.wikipedia.org/wiki/Meltdown_(security_v...
    Reply
  • iwod - Monday, August 20, 2018 - link

    When Zen 2 comes, which is going to be slightly later than CLake I think, please test Clake with all those security measures fix and see how it fare against AMD. Reply
  • moozooh - Monday, August 20, 2018 - link

    So does this mean the Optane DIMMs won't be compatible with the consumer CPUs / chipset families? Cause I'd love to have it as a universal in-hardware RAM drive alternative with comparable latencies and IOPS performance but more convenience and far less compatibility issues. Reply
  • edzieba - Monday, August 20, 2018 - link

    We've known that for quite some time: the Optane DIMMs require dedicated hardware in the processor (where the memory controllers are) which is only currently present in Xeon scalable CPUs. Reply
  • HStewart - Monday, August 20, 2018 - link

    This is exactly wanted to here about the Spectrum - Meltdown stuff - we all know it that Intel has been under stress about this and the delay of 10nm - but some have reported that the hardware changes would be delay until 10nm - so this means that Intel does not have to have all 10nm to make those changes in hard. So 14nm++ or what every people is not same architecture as previous chips. To me it obvious that Intel has put fixing these security issues top priority.

    As for some of problems requiring OS/VMM - as a former OS developer, it very possible that volubility is in designed of OS - Intel has given OS developers like Microsoft, Apple - and unix base community software recommendations for changes in code to prevent them in current hard.
    Reply
  • wpapolis - Monday, August 20, 2018 - link

    “Showing the Ankle” and “drip feeding”? You r mixing your metaphors. You need to focus on one theme like ... “raising it’s skirt”, “showing more leg” ... u know ... like that! 👍 Another great article ... now let me get back to reading the rest! Haha Reply
  • Kevin G - Monday, August 20, 2018 - link

    Intel did do something tricky in that while LGA 3647 exposes 48 PCIe lanes, the HCC and XCC dies actually contain 64 lane PCIe controller. The 16 lanes are for on package accelerators or fabric. While I doubt Intel did increase this figures (or add an on-die UPI link), their wording appears to keep that possibility open. Reply
  • nirmal12 - Monday, October 08, 2018 - link

    For those people expecting an IDF-like substantial talk about the chips. The question arising are how the SKUs will be separated, How product stack will look like etc. I also think Intel will be drip feeding information about Cascade Lake. Reply

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