AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm
by Ian Cutress on February 1, 2018 8:45 AM ESTOver the years we have seen various attempts from AMD and Intel to try and help improve storage performance on their mainstream platforms. Because of the solid user experience benefits that solid state storage can bring, these attempts come in two forms: to make the most of a small amount of super-fast storage, or to expand the amount of super-fast storage available. Most attempts at this have been laborious, such as Intel’s caching technology that allows a SSD or 32GB of Optane Memory to act as a quick read/write cache for a rotational drive.
AMD’s latest attempt to boost the storage performance is Enmotus FuzeDrive, a collaborative piece of software that is designed to combine several storage devices into one big disk. The principle is fairly simple: take any combination of rotational hard drive, SATA SSD, NVMe SSD, and even DRAM, and this software will create a single drive that addresses them all. The software and drivers will manage what data goes where for quicker access, rather than it appearing as one big JBOD.
The obvious red flags from the press were about DRAM, which we were told will only act as a read-cache from prepared data taken from the other drives. The other flag was about if one drive in that system fails, whether all the data is lost. The answer was a likely yes, and so the risk of such a system might be in-line with a JBOD array or similar to a RAID-0, but without the predictable speedup a RAID-0 array might bring.
Predictive caching technologies to help speed up read/write access times are, on paper, a good idea. Some SSDs already do this, by having a small amount of fast SLC cache to act as a write buffer, which the controller can then move the data around to empty the cache when the drive is idle. The difference between having something like a controller manage an embedded system and a general software package in play is that the embedded system has to work for a single drive, albeit millions of units. That arrangement is going to be as defined and engineered as much as that SSD vendor wants it to be. For a software package, it has to work across a variety of environments that might be badly configured, or in situations that the software might not be able to identify properly. As the software stretches over three or four different drives, it sounds like a potential failure in the making of one of those drives decides to die.
AMD lists several benefits of FuzeDrive: no Windows reinstall required, drives can be added to the pool at any point, or removed from the pool if sufficient spare space exists. Pools with DRAM added can be configured manually if some more DRAM is needed. AMD lists that in its testing, comparing a 500 GB hard-drive to a system with a Samsung 960 Pro added to the pool, they recorded a 578% faster Adobe Premiere launch, and a 931% faster Adobe Photoshop launch.
I could see FuzeDrive being useful in two particular scenarios: If a user as a small (32-128 GB) NVMe drive and a 1TB SSD/HDD, a single pool can be made. Users with a single large drive (SATA or HDD) could use the software to add DRAM, enabling an automatic RAM disk.
Enmotus FuzeDrive will be available for Ryzen Desktop systems, and will cost $20.
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mateau - Monday, January 8, 2018 - link
@Ian ..."It is our understanding that the 12nm process is essentially a 14+ process for GloFo"
Would you please a credible source for that statement. Say, EETimes or other such Industry outlet rather than an garnished from sites who do nothing other than plagiarize work that fits into the point they are try to make.
I too have read on-line media's dismissal of GloFo 12nm process. Everything that I have read on this matter is based upon an early on-line media piece highly critical to AMD that tried to minimize the impact of 12nm. GloFo on their website specifically states that 12nm is a NEW process node and it is 12nm. GloFo has announced that 12nm IS 12nm, a new shrink from 14nm. Announcing falsely would create all sorts of problems with the FTC and lawyers who do nothing but specialize in Class Action suits. Case in point Intel is getting it's clock cleaned due to their knowledge of and failure to eliminate the Meltdown hardware flaw.
As with ALL process nodes, the entire die is not fabbed with say 12nm or 14nm or for that matter the upcoming 7nm node. There are components within the die that can be and sometimes must be greater in size than the process node taped out for the silicon.
Perhaps you shaould also take the time to ask Dr. Su directly if ONE DESIGN covers ALL EPYC, RYZEN and Threadripper design? In my opinion EPYC is a design similar to Zeppelin and Ryzen but with some major design differences that make a server processor.
No sense speculating on something if you can ask AMD CEO directly.
A5 - Monday, January 8, 2018 - link
They may have been able to reduce the minimum possible feature size in a way that lets them claim a new number, but that doesn't necessarily mean that the performance of a finished product is significantly different.It's impossible to know until products are out in the world, because all we have for now is GloFo PR statements, which are going to make things look as rosy as possible.
SaturnusDK - Monday, January 8, 2018 - link
The Zeppelin die covers all Ryzen, Ryzen Pro, Threadripper, and EPYC CPUs. However, there are parts disabled on those designated Ryzen and Threadripper that are enabled on Ryzen Pro and EPYC. I do not know for certain if there is any feature differences between Ryzen Pro and EPYC but judging from AMDs own information there doesn't seem to be.Dr. Swag - Monday, January 8, 2018 - link
https://www.anandtech.com/show/11854/globalfoundri...based on improvements in the 10-20% range calling it "essentially a 14nm+ node" seems reasonable to me.
iwod - Monday, January 8, 2018 - link
Huh?Meltdown - Not relevant here.
TSMC called their 16nm++ ( or was it 16nm +++ ) as 12nm.
And FTC would have a problem with Intel because their 10nm really should be 7nm by Fab Industry measurement.
And it is not garish, it is straight from GF investor conference.
Design? Speculate? Is Goldmount the same design as Goldmount+. Do QA and feature / yield test accounts for design? And more importantly, do even any other chip maker disclose these information? There is something call trade secret.
LurkingSince97 - Thursday, January 18, 2018 - link
It is well known knowledge that GloFlo 're-branded' their 14nm+ to 12nm.There is nearly a dozen different feature sizes in a process these days, no one number captures it.
Also, GloFlo is not the only one that has done this sort of thing.
LurkingSince97 - Thursday, January 18, 2018 - link
To be more specific, GloFo's own conference / announcement talked about the name change... AMD's roadmaps had "Zen+" on a GloFo 14nm+ node, then suddenly that same roadmap changed it to "12nm" when GloFo announced the new node (and named it)coolhardware - Monday, January 8, 2018 - link
Get well soon Ian!Luposian - Wednesday, January 10, 2018 - link
Wouldn't now be a perfect time to implement changes to the predictive branch execution portions of the new processors, to eliminate issues with Spectre and Meltdown, since they're just making these processors now?LurkingSince97 - Thursday, January 18, 2018 - link
They have _finished_ the Zen 2 design. Zen already doesn't have problems with Meltdown. Spectre is a lot harder to do anything about, other than maybe adding an instruction for a branch prediction barrier. Maybe they had time to add that to Zen 2, or maybe it can be done even in Zen+ without much trouble. Your software will need to be recompiled against it, however.