I Keep My Cache Private

As mentioned in the original Skylake-X announcements, the new Skylake-SP cores have shaken up the cache hierarchy compared to previous generations. What used to be simple inclusive caches have now been adjusted in size, policy, latency, and efficiency, which will have a direct impact on performance. It also means that Skylake-S and Skylake-SP will have different instruction throughput efficiency levels. They could be the difference between chalk and cheese and a result, or the difference between stilton and aged stilton.

Let us start with a direct compare of Skylake-S and Skylake-SP.

Comparison: Skylake-S and Skylake-SP Caches
Skylake-S Features Skylake-SP
32 KB
4KB 64-entry 4-way TLB
L1-D 32 KB
4KB 64-entry 4-way TLB
32 KB
4KB 128-entry 8-way TLB
L1-I 32 KB
4KB 128-entry 8-way TLB
256 KB
4KB 1536-entry 12-way TLB
L2 1 MB
11-13 cycle
4KB 1536-entry 12-way TLB
< 2 MB/core
Up to 16-way
L3 1.375 MB/core

The new core keeps the same L1D and L1I cache structures, both implementing writeback 32KB 8-way caches for each. These caches have a 4-cycle access latency, but differ in their access support: Skylake-S does 2x32-byte loads and 1x32-byte store per cycle, whereas Skylake-SP offers double on both.

The big changes are with the L2 and the L3. Skylake-SP has a 1MB private L2 cache with 16-way associativity, compared to the 256KB private L2 cache with 4-way associativity in Skylake-S. The L3 changes to an 11-way non-inclusive 1.375MB/core, from a 20-way fully-inclusive 2.5MB/core arrangement.

That’s a lot to unpack, so let’s start with inclusivity:

Inclusive Caching

An inclusive cache contains everything in the cache underneath it and has to be at least the same size as the cache underneath (and usually a lot bigger), compared to an exclusive cache which has none of the data in the cache underneath it. The benefit of an inclusive cache means that if a line in the lower cache is removed due it being old for other data, there should still be a copy in the cache above it which can be called upon. The downside is that the cache above it has to be huge – with Skylake-S we have a 256KB L2 and a 2.5MB/core L3, meaning that the L2 data could be replaced 10 times before a line is evicted from the L3.

A non-inclusive cache is somewhat between the two, and is different to an exclusive cache: in this context, when a data line is present in the L2, it does not immediately go into L3. If the value in L2 is modified or evicted, the data then moves into L3, storing an older copy. (The reason it is not called an exclusive cache is because the data can be re-read from L3 to L2 and still remain in the L3). This is what we usually call a victim cache, depending on if the core can prefetch data into L2 only or L2 and L3 as required. In this case, we believe the SKL-SP core cannot prefetch into L3, making the L3 a victim cache similar to what we see on Zen, or Intel’s first eDRAM parts on Broadwell. Victim caches usually have limited roles, especially when they are similar in size to the cache below it (if a line is evicted from a large L2, what are the chances you’ll need it again so soon), but some workloads that require a large reuse of recent data that spills out of L2 will see some benefit.

So why move to a victim cache on the L3? Intel’s goal here was the larger private L2. By moving from 256KB to 1MB, that’s a double double increase. A general rule of thumb is that a doubling of the cache increases the hit rate by 41% (square root of 2), which can be the equivalent to a 3-5% IPC uplift. By doing a double double (as well as doing the double double on the associativity), Intel is effectively halving the L2 miss rate with the same prefetch rules. Normally this benefits any L2 size sensitive workloads, which some enterprise environments such as databases can be L2 size sensitive (and we fully suspect that a larger L2 came at the request of the cloud providers).

Moving to a larger cache typically increases latency. Intel is stating that the L2 latency has increased, from 11 cycles to ~13, depending on the type of access – the fastest load-to-use is expected to be 13 cycles. Adjusting the latency of the L2 cache is going to have a knock-on effect given that codes that are not L2 size sensitive might still be affected.

So if the L2 is larger and has a higher latency, does that mean the smaller L3 is lower latency? Unfortunately not, given the size of the L2 and a number of other factors – with the L3 being a victim cache, it is typically used less frequency so Intel can give the L3 less stringent requirements to remain stable. In this case the latency has increased from 44 in SKL-X to 77 in SKL-SP. That’s a sizeable difference, but again, given the utility of the victim cache it might make little difference to most software.

Moving the L3 to a non-inclusive cache will also have repercussions for some of Intel’s enterprise features. Back at the Broadwell-EP Xeon launch, one of the features provided was L3 cache partitioning, allowing limited size virtual machines to hog most of the L3 cache if it was running a mission-critical workflow. Because the L3 cache was more important, this was a good feature to add. Intel won’t say how this feature has evolved with the Skylake-SP core at this time, as we will probably have to wait until that launch to find out.

As a side note, it is worth noting here that Broadwell-E was a 256KB private L2 but 8-way, compared to Skylake-S which was a 256KB private L2 but 4-way. Intel stated that the Skylake-S base core went down in associativity for several reasons, but the main one was to make the design more modular. In this case it means the L2 in both size and associativity are 4x from Skylake-S by design, and shows that there may be 512KB 8-way variants in the future.

Microarchitecture Analysis: Adding in AVX-512 and Tweaks to Skylake-S Intel Makes a Mesh: New Core-to-Core Communication Paradigm


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  • Gastec - Sunday, August 20, 2017 - link

    The Ryzen 1600X has the same theoretical frequencies as 1800X (on paper) minus 2 cores. Both Ryzen 1700X and 1700 have lower frequencies than 1600X. As to why the 1600X shows slightly better results than 1800X in some single-core tests it's probably due to a combination of lower power consumption(less heat) XFR and binning.
    Read this: http://www.anandtech.com/show/11244/the-amd-ryzen-...
  • dstephens80 - Monday, August 14, 2017 - link

    All, I have come across something interesting and wondering if it is only me. I just received my 7820x and was playing around with overclocking and I have to question Intel's claim that the CPUs are "Fully Unlocked". Using an Asus Strix-E X299 MB I adjusted my overclock to 4.6Ghz and then booted successfully and started my stress testing. I noticed my clock speed was bouncing between 4.3 and 4.6 so I thought maybe speedstep was interfering and went into BIOS and turned off SpeedStep, TurboBoost and C-states. When I booted back up I received an error for the TurboBoost utility (expected) but my speed was at the stock 3.6Ghz and the Intel Extreme Utility showed the same but also showed my multiplier should be set at 46. I went back into BIOS and enabled "TurboBoost" and upon reboot CPUz/Intel utility both showed speed at 4.6Ghz. My issue with the "Fully Unlocked" claim is that an OC should not be dependent on a software driver. I have confimed this by the fact that when I boot Linux the OC is not applied. Reply
  • leeymcj - Sunday, September 3, 2017 - link

    I have a question, so all the cores are equipped with dedicated AVX register? (cost ~15% of area for each of them) Reply
  • gogi95 - Wednesday, September 27, 2017 - link

    what is replacement algorithm used in Intel core i9? Reply

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