AMD's EPYC Server CPU

If you have read Ian's articles about Zen and EPYC in detail, you can skip this page. For those of you who need a refresher, let us quickly review what AMD is offering. 

The basic building block of EPYC and Ryzen is the CPU Complex (CCX), which consists of 4 vastly improved "Zen" cores, connected to an L3-cache. In a full configuration each core technically has its own 2 MB of L3, but access to the other 6 MB is rather speedy. Within a CCX we measured 13 ns to access the first 2 MB, and 15 to 19 ns for the rest of the 8 MB L3-cache, a difference that's hardly noticeable in the grand scheme of things. The L3-cache acts as a mostly exclusive victim cache. 

Two CCXes make up one Zeppelin die. A custom fabric – AMD's Infinity Fabric – ties together two CCXes, the two 8 MB L3-caches, 2 DDR4-channels, and the integrated PCIe lanes. That topology is not without some drawbacks though: it means that there are two separate 8 MB L3 caches instead of one single 16 MB LLC. This has all kinds of consequences. For example the prefetchers of each core make sure that data of the L3 is brought into the L1 when it is needed. Meanwhile each CCX has its own separate (not inside the L3, so no capacity hit) and dedicated SRAM snoop directory (keeping track of 7 possible states). In other words, the local L3-cache communicates very quickly with everything inside the same CCX, but every data exchange between two CCXes comes with a tangible latency penalty. 

Moving further up the chain, the complete EPYC chip is a Multi Chip Module(MCM) containing 4 Zeppelin dies.

AMD made sure that each die is only one hop apart from the other, ensuring that the off-die latency is as low as reasonably possible.

Meanwhile scaling things up to their logical conclusion, we have 2P configurations. A dual socket EPYC setup is in fact a "virtual octal socket" NUMA system. 

AMD gave this "virtual octal socket" topology ample bandwidth to communicate. The two physical sockets are connected by four bidirectional interconnects, each consisting of 16 PCIe lanes. Each of these interconnect links operates at +/- 38 GB/s (or 19 GB/s in each direction). 

So basically, AMD's topology is ideal for applications with many independently working threads such as small VMs, HPC applications, and so on. It is less suited for applications that require a lot of data synchronization such as transactional databases. In the latter case, the extra latency of exchanging data between dies and even CCX is going to have an impact relative to a traditional monolithic design.

Tensions (And Chip Sizes) Are Rising AMD’s EPYC 7000-Series Processors
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  • Kaotika - Tuesday, July 11, 2017 - link

    http://www.anandtech.com/show/11464/intel-announce...
    This one remains wrong though
    Reply
  • Ian Cutress - Tuesday, July 11, 2017 - link

    Always reference the newest piece, especially the main review.
    Or we'd spend half of our time going back and updating old pieces and reviews with new data.
    Reply
  • scottb9239 - Tuesday, July 11, 2017 - link

    On the POV-RAY benchmark, shouldn't that read as almost 16% faster than the dual 2699 v4 and 32% faster than the dual 8176? Reply
  • scienceomatica - Tuesday, July 11, 2017 - link

    I think that a fair game would be to compare the top offer of one and the other manufacturer, in other words, the Xeon 8180 should be included in the benchmark regardless of the aspect of the price. Then the difference would be quite in favor of the Intel processor, although it has few cores less. Reply
  • Tamz_msc - Tuesday, July 11, 2017 - link

    Will we get to see more FP HPC-oriented workloads like SPECfp2006 or even 2017 being discussed in a future article? Reply
  • lefty2 - Tuesday, July 11, 2017 - link

    I can summarize this article: "$8719 chip beaten by $4200 chip in everything except database and Appache spark."
    Well done Intel, another Walletripper!
    Reply
  • Shankar1962 - Wednesday, July 12, 2017 - link

    Then why did google att aws etc upgraded to skylake. They could have saved billions of dollars. Reply
  • Shankar1962 - Wednesday, July 12, 2017 - link

    Look at what big players upgrading to skylake reported
    These are real workloads
    No one cares about labs
    These numbers decide who wins and who loses
    No wonder AMD sells at $4200

    https://www.google.com/amp/s/seekingalpha.com/amp/...
    Reply
  • nitrobg - Tuesday, July 11, 2017 - link

    Pricing on page 10 should reflect that the 2P EPYC prices are for 2 processors, not per CPU. The price of Xeons is per CPU. Reply
  • coder543 - Tuesday, July 11, 2017 - link

    That doesn't seem true. The prices they currently have seem to be correct. Got a source? Reply

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