Memory Subsystem: Latency

The performance of modern CPUs depends heavily on the cache subsystem. And some applications depend heavily on the DRAM subsystem too. We used LMBench in an effort to try to measure cache and memory latency. The numbers we looked at were "Random load latency stride=16 Bytes".

Mem
Hierarchy
AMD EPYC 7601
DDR4-2400
Intel Skylake-SP
DDR4-2666
Intel Broadwell
Xeon E5-2699v4
DDR4-2400
L1 Cache cycles 4
L2 Cache cycles  12 14-22  12-15
L3 Cache 4-8 MB - cycles 34-47 54-56 38-51
16-32 MB - ns 89-95 ns 25-27 ns
(+/- 55 cycles?)
27-42 ns
(+/- 47 cycles)
Memory 384-512 MB - ns 96-98 ns 89-91 ns 95 ns

Previously, Ian has described the AMD Infinity Fabric that stitches the two CCXes together in one die and interconnects the 4 different "Zeppelin" dies in one MCM. The choice of using two CCXes in a single die is certainly not optimal for Naples. The local "inside the CCX" 8 MB L3-cache is accessed with very little latency. But once the core needs to access another L3-cache chunk – even on the same die – unloaded latency is pretty bad: it's only slightly better than the DRAM access latency. Accessing DRAM is on all modern CPUs a naturally high latency operation: signals have to travel from the memory controller over the memory bus, and the internal memory matrix of DDR4-2666 DRAM is only running at 333 MHz (hence the very high CAS latencies of DDR4). So it is surprising that accessing SRAM over an on-chip fabric requires so many cycles. 

What does this mean to the end user? The 64 MB L3 on the spec sheet does not really exist. In fact even the 16 MB L3 on a single Zeppelin die consists of two 8 MB L3-caches. There is no cache that truly functions as single, unified L3-cache on the MCM; instead there are eight separate 8 MB L3-caches. 

That will work out fine for applications that have a footprint that fits within a single 8 MB L3 slice, like virtual machines (JVM, Hypervisors based ones) and HPC/Big Data applications that work on separate chunks of data in parallel (for example, the "map" phase of "map/reduce"). However this kind of setup will definitely hurt the performance of applications that need "central" access to one big data pool, such as database applications and big data applications in the "Shuffle phase". 

Memory Subsystem: TinyMemBench

To double check our latency measurements and get a deeper understanding of the respective architectures, we also use the open source TinyMemBench benchmark. The source was compiled for x86 with GCC 5.4 and the optimization level was set to "-O3". The measurement is described well by the manual of TinyMemBench:

Average time is measured for random memory accesses in the buffers of different sizes. The larger the buffer, the more significant the relative contributions of TLB, L1/L2 cache misses, and DRAM accesses become. All the numbers represent extra time, which needs to be added to L1 cache latency (4 cycles).

We tested with dual random read, as we wanted to see how the memory system coped with multiple read requests. 

L3-cache sizes have increased steadily over the years. The Xeon E5 v1 had up to 20 MB, v3 came with 45 MB, and v4 "Broadwell EP" further increased this to 55 MB. But the fatter the cache, the higher the latency became. L3 latency doubled from Sandy Bridge-EP to Broadwell-EP.  So it is no wonder that Skylake went for a larger L2-cache and a smaller but faster L3. The L2-cache offers 4 times lower latency at 512 KB. 

AMD's unloaded latency is very competitive under 8 MB, and is a vast improvement over previous AMD server CPUs. Unfortunately, accessing more 8 MB incurs worse latency than a Broadwell core accessing DRAM. Due to the slow L3-cache access, AMD's DRAM access is also the slowest. The importance of unloaded DRAM latency should of course not be exaggerated: in most applications most of the loads are done in the caches. Still, it is bad news for applications with pointer chasing or other latency-sensitive operations. 

Memory Subsystem: Bandwidth Single Threaded Integer Performance: SPEC CPU2006
POST A COMMENT

219 Comments

View All Comments

  • Ian Cutress - Tuesday, July 11, 2017 - link

    We corrected that in our Skylake-X review. Reply
  • Kaotika - Tuesday, July 11, 2017 - link

    http://www.anandtech.com/show/11464/intel-announce...
    This one remains wrong though
    Reply
  • Ian Cutress - Tuesday, July 11, 2017 - link

    Always reference the newest piece, especially the main review.
    Or we'd spend half of our time going back and updating old pieces and reviews with new data.
    Reply
  • scottb9239 - Tuesday, July 11, 2017 - link

    On the POV-RAY benchmark, shouldn't that read as almost 16% faster than the dual 2699 v4 and 32% faster than the dual 8176? Reply
  • scienceomatica - Tuesday, July 11, 2017 - link

    I think that a fair game would be to compare the top offer of one and the other manufacturer, in other words, the Xeon 8180 should be included in the benchmark regardless of the aspect of the price. Then the difference would be quite in favor of the Intel processor, although it has few cores less. Reply
  • Tamz_msc - Tuesday, July 11, 2017 - link

    Will we get to see more FP HPC-oriented workloads like SPECfp2006 or even 2017 being discussed in a future article? Reply
  • lefty2 - Tuesday, July 11, 2017 - link

    I can summarize this article: "$8719 chip beaten by $4200 chip in everything except database and Appache spark."
    Well done Intel, another Walletripper!
    Reply
  • Shankar1962 - Wednesday, July 12, 2017 - link

    Then why did google att aws etc upgraded to skylake. They could have saved billions of dollars. Reply
  • Shankar1962 - Wednesday, July 12, 2017 - link

    Look at what big players upgrading to skylake reported
    These are real workloads
    No one cares about labs
    These numbers decide who wins and who loses
    No wonder AMD sells at $4200

    https://www.google.com/amp/s/seekingalpha.com/amp/...
    Reply
  • nitrobg - Tuesday, July 11, 2017 - link

    Pricing on page 10 should reflect that the 2P EPYC prices are for 2 processors, not per CPU. The price of Xeons is per CPU. Reply

Log in

Don't have an account? Sign up now