Sizing Up Servers: Intel's Skylake-SP Xeon versus AMD's EPYC 7000 - The Server CPU Battle of the Decade?
by Johan De Gelas & Ian Cutress on July 11, 2017 12:15 PM EST- Posted in
- CPUs
- AMD
- Intel
- Xeon
- Enterprise
- Skylake
- Zen
- Naples
- Skylake-SP
- EPYC
Memory Subsystem: Bandwidth
Measuring the full bandwidth potential with John McCalpin's Stream bandwidth benchmark is getting increasingly difficult on the latest CPUs, as core and memory channel counts have continued to grow. We compiled the stream 5.10 source code with the Intel compiler (icc) for linux version 17, or GCC 5.4, both 64-bit. The following compiler switches were used on icc:
icc -fast -qopenmp -parallel (-AVX) -DSTREAM_ARRAY_SIZE=800000000
Notice that we had to increase the array significantly, to a data size of around 6 GB. We compiled one version with AVX and one without.
The results are expressed in gigabytes per second.
Meanwhile the following compiler switches were used on gcc:
-Ofast -fopenmp -static -DSTREAM_ARRAY_SIZE=800000000
Notice that the DDR4 DRAM in the EPYC system ran at 2400 GT/s (8 channels), while the Intel system ran its DRAM at 2666 GT/s (6 channels). So the dual socket AMD system should theoretically get 307 GB per second (2.4 GT/s* 8 bytes per channel x 8 channels x 2 sockets). The Intel system has access to 256 GB per second (2.66 GT/s* 8 bytes per channel x 6 channels x 2 sockets).
AMD told me they do not fully trust the results from the binaries compiled with ICC (and who can blame them?). Their own fully customized stream binary achieved 250 GB/s. Intel claims 199 GB/s for an AVX-512 optimized binary (Xeon E5-2699 v4: 128 GB/s with DDR-2400). Those kind of bandwidth numbers are only available to specially tuned AVX HPC binaries.
Our numbers are much more realistic, and show that given enough threads, the 8 channels of DDR4 give the AMD EPYC server a 25% to 45% bandwidth advantage. This is less relevant in most server applications, but a nice bonus in many sparse matrix HPC applications.
Maximum bandwidth is one thing, but that bandwidth must be available as soon as possible. To better understand the memory subsystem, we pinned the stream threads to different cores with numactl.
Pinned Memory Bandwidth (in MB/sec) | |||
Mem Hierarchy |
AMD "Naples" EPYC 7601 DDR4-2400 |
Intel "Skylake-SP" Xeon 8176 DDR4-2666 |
Intel "Broadwell-EP" Xeon E5-2699v4 DDR4-2400 |
1 Thread | 27490 | 12224 | 18555 |
2 Threads, same core same socket |
27663 | 14313 | 19043 |
2 Threads, different cores same socket |
29836 | 24462 | 37279 |
2 Threads, different socket | 54997 | 24387 | 37333 |
4 threads on the first 4 cores same socket |
29201 | 47986 | 53983 |
8 threads on the first 8 cores same socket |
32703 | 77884 | 61450 |
8 threads on different dies (core 0,4,8,12...) same socket |
98747 | 77880 | 61504 |
The new Skylake-SP offers mediocre bandwidth to a single thread: only 12 GB/s is available despite the use of fast DDR-4 2666. The Broadwell-EP delivers 50% more bandwidth with slower DDR4-2400. It is clear that Skylake-SP needs more threads to get the most of its available memory bandwidth.
Meanwhile a single thread on a Naples core can get 27,5 GB/s if necessary. This is very promissing, as this means that a single-threaded phase in an HPC application will get abundant bandwidth and run as fast as possible. But the total bandwidth that one whole quad core CCX can command is only 30 GB/s.
Overall, memory bandwidth on Intel's Skylake-SP Xeon behaves more linearly than on AMD's EPYC. All off the Xeon's cores have access to all the memory channels, so bandwidth more directly increases with the number of threads.
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Kaotika - Tuesday, July 11, 2017 - link
http://www.anandtech.com/show/11464/intel-announce...This one remains wrong though
Ian Cutress - Tuesday, July 11, 2017 - link
Always reference the newest piece, especially the main review.Or we'd spend half of our time going back and updating old pieces and reviews with new data.
scottb9239 - Tuesday, July 11, 2017 - link
On the POV-RAY benchmark, shouldn't that read as almost 16% faster than the dual 2699 v4 and 32% faster than the dual 8176?scienceomatica - Tuesday, July 11, 2017 - link
I think that a fair game would be to compare the top offer of one and the other manufacturer, in other words, the Xeon 8180 should be included in the benchmark regardless of the aspect of the price. Then the difference would be quite in favor of the Intel processor, although it has few cores less.Tamz_msc - Tuesday, July 11, 2017 - link
Will we get to see more FP HPC-oriented workloads like SPECfp2006 or even 2017 being discussed in a future article?lefty2 - Tuesday, July 11, 2017 - link
I can summarize this article: "$8719 chip beaten by $4200 chip in everything except database and Appache spark."Well done Intel, another Walletripper!
Shankar1962 - Wednesday, July 12, 2017 - link
Then why did google att aws etc upgraded to skylake. They could have saved billions of dollars.Shankar1962 - Wednesday, July 12, 2017 - link
Look at what big players upgrading to skylake reportedThese are real workloads
No one cares about labs
These numbers decide who wins and who loses
No wonder AMD sells at $4200
https://www.google.com/amp/s/seekingalpha.com/amp/...
nitrobg - Tuesday, July 11, 2017 - link
Pricing on page 10 should reflect that the 2P EPYC prices are for 2 processors, not per CPU. The price of Xeons is per CPU.coder543 - Tuesday, July 11, 2017 - link
That doesn't seem true. The prices they currently have seem to be correct. Got a source?