SMT Integer Performance With SPEC CPU2006

Next, to test the performance impact of simultaneous multithreading (SMT) on a single core, we test with two threads on the same core. This way we can evaluate how well the core handles SMT. 

Subtest Application type Xeon E5-2690 @ 3.8 Xeon E5-2690 v3 @ 3.5 Xeon E5-2699 v4 @ 3.6 EPYC 7601 @3.2 Xeon 8176 @ 3.8
400.perlbench Spam filter 39.8 43.9 47.2 40.6 55.2
401.bzip2 Compression 32.6 32.3 32.8 33.9 34.8
403.gcc Compiling 40.7 43.8 32.5 41.6 32.1
429.mcf Vehicle scheduling 44.7 51.3 55.8 44.2 56.6
445.gobmk Game AI 36.6 35.9 38.1 36.4 39.4
456.hmmer Protein seq. analyses 32.5 34.1 40.9 34.9 44.3
458.sjeng Chess 36.4 36.9 39.5 36 41.9
462.libquantum Quantum sim 75 73.4 89 89.2 91.7
464.h264ref Video encoding 52.4 58.2 58.5 56.1 75.3
471.omnetpp Network sim 25.4 30.4 48.5 26.6 42.1
473.astar Pathfinding 31.4 33.6 36.6 29 37.5
483.xalancbmk XML processing 43.7 53.7 78.2 37.8 78

Now on a percentage basis versus the single-threaded results, so that we can see how much performance we gained from enabling SMT:

Subtest Application type Xeon E5-2699 v4 @ 3.6 EPYC 7601 @3.2 Xeon 8176 @ 3.8
400.perlbench Spam filter 109% 131% 110%
401.bzip2 Compression 137% 141% 128%
403.gcc Compiling 137% 119% 131%
429.mcf Vehicle scheduling 125% 110% 131%
445.gobmk Game AI 125% 150% 127%
456.hmmer Protein seq. analyses 127% 125% 125%
458.sjeng Chess 120% 151% 125%
462.libquantum Quantum sim 91% 129% 90%
464.h264ref Video encoding 101% 112% 112%
471.omnetpp Network sim 109% 116% 103%
473.astar Pathfinding 140% 149% 137%
483.xalancbmk XML processing 120% 107% 116%

On average, both Xeons pick up about 20% due to SMT (Hyperthreading). The EPYC 7601 improved by even more: it gets a 28% boost on average. There are many possible explanations for this, but two are the most likely. In the situation where AMD's single threaded IPC is very low because it is waiting on the high latency of a further away L3-cache (>8 MB), a second thread makes sure that the CPU resources can be put to better use (like compression, the network sim). Secondly, we saw that AMD core is capable of extracting more memory bandwidth in lightly threaded scenarios. This might help in the benchmarks that stress the DRAM (like video encoding, quantum sim). 

Nevertheless, kudos to the AMD engineers. Their first SMT implementation is very well done and offers a tangible throughput increase. 

Single Threaded Integer Performance: SPEC CPU2006 Multi-core SPEC CPU2006
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  • psychobriggsy - Tuesday, July 11, 2017 - link

    Indeed it is a ridiculous comment, and puts the earlier crying about the older Ubuntu and GCC into context - just an Intel Fanboy.

    In fact Intel's core architecture is older, and GCC has been tweaked a lot for it over the years - a slightly old GCC might not get the best out of Skylake, but it will get a lot. Zen is a new core, and GCC has only recently got optimisations for it.
    Reply
  • EasyListening - Wednesday, July 12, 2017 - link

    I thought he was joking, but I didn't find it funny. So dumb.... makes me sad. Reply
  • blublub - Tuesday, July 11, 2017 - link

    I kinda miss Infinity Fabric on my Haswell CPU and it seems to only have on die - so why is that missing on Haswell wehen Ryzen is an exact copy? Reply
  • blublub - Tuesday, July 11, 2017 - link

    Your actually sound similar to JuanRGA at SA Reply
  • Kevin G - Wednesday, July 12, 2017 - link

    @CajunArson The cache hierarchy is radically different between these designs as well as the port arrangement for dispatch. Scheduling on Ryzen is split between execution resources where as Intel favors a unified approach. Reply
  • bill.rookard - Tuesday, July 11, 2017 - link

    Well, that is something that could be figured out if they (anandtech) had more time with the servers. Remember, they only had a week with the AMD system, and much like many of the games and such, optimizing is a matter of run test, measure, examine results, tweak settings, rinse and repeat. Considering one of the tests took 4 hours to run, having only a week to do this testing means much of the optimization is probably left out.

    They went with a 'generic' set of relative optimizations in the interest of time, and these are the (very interesting) results.
    Reply
  • CoachAub - Wednesday, July 12, 2017 - link

    Benchmarks just need to be run on as level as a field as possible. Intel has controlled the market so long, software leans their way. Who was optimizing for Opteron chips in 2016-17? ;) Reply
  • theeldest - Tuesday, July 11, 2017 - link

    The compiler used isn't meant to be the the most optimized, but instead it's trying to be representative of actual customer workloads.

    Most customer applications in normal datacenters (not google, aws, azure, etc) are running binaries that are many years behind on optimizations.

    So, yes, they can get better performance. But using those optimizations is not representative of the market they're trying to show numbers for.
    Reply
  • CajunArson - Tuesday, July 11, 2017 - link

    That might make a tiny bit of sense if most of the benchmarks run were real-world workloads and not C-Ray or POV-Ray.

    The most real-world benchmark in the whole setup was the database benchmark.
    Reply
  • coder543 - Tuesday, July 11, 2017 - link

    The one benchmark that favors Intel is the "most real-world"? Absolutely, I want AnandTech to do further testing, but your comments do not sound unbiased. Reply

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