Intel's Optimized Turbo Profiles

Also new to Skylake-SP, Intel has also further enhanced turbo boosting.

There are also some security and virtualization enhancements (MBE, PPK, MPX) , but these are beyond the scope this article as we don't test them. 

Summing It All Up: How Skylake-SP and Zen Compare

The table below shows you the differences in a nutshell.

  AMD EPYC 7000
 
Intel Skylake-SP Intel Broadwell-EP
 
Package & Dies Four dies in one MCM Monolithic  Monolithic
Die size 4x 195 mm² 677 mm² 456 mm²
On-Chip Topology Infinity Fabric
(1-Hop Max)
Mesh Dual Ring
Socket configuration 1-2S 1-8S ("Platinum") 1-2S
Interconnect (Max.)
Bandwidth (*)(Max.)
4x16 (64) PCIe lanes
4x 37.9 GB/s
3x UPI 20 lanes
3x 41.6 GB/s
2x QPI 20 lanes
2x 38.4 GB/s
TDP 120-180W 70-205W 55-145W
8-32 4-28 4-22
LLC (max.) 64MB (8x8 MB) 38.5 MB 55 MB
Max. Memory 2 TB 1.5 TB 1.5 TB
Memory subsystem
Fastest sup. DRAM
8 channels
DDR4-2666
6 channels
DDR4-2666
4 channels
DDR4-2400
PCIe Per CPU in a 2P 64 PCIe (available) 48 PCIe 3.0 40 PCIe 3.0

(*) total bandwidth (bidirectional)

At a high level, I would argue that Intel has the most advanced multi-core topology, as they're capable of integrating up to 28 cores in a mesh. The mesh topology will allow Intel to add more cores in future generations while scaling consistently in most applications. The last level cache has a decent latency and can accommodate applications with a massive memory footprint. The latency difference between accessing a local L3-cache chunk and one further away is negligible on average, allowing the L3-cache to be a central storage for fast data synchronization between the L2-caches. However, the highest performing Xeons are huge, and thus expensive to manufacture. 

AMD's MCM approach is much cheaper to manufacture. Peak memory bandwidth and capacity is quite a bit higher with 4 dies and 2 memory channels per die. However, there is no central last level cache that can perform low latency data coordination between the L2-caches of the different cores (except inside one CCX). The eight 8 MB L3-caches acts like - relatively low latency - spill over caches for the 32 L2-caches on one chip.  

Intel's New On-Chip Topology: A Mesh Xeon Skylake-SP SKUs
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  • tamalero - Tuesday, July 11, 2017 - link

    How is that different if AMD ran stuff that is extremely optimized for them?
  • Friendly0Fire - Tuesday, July 11, 2017 - link

    That's kinda the point? You want to benchmark the CPUs in optimal scenarios, since that's what you'd be looking at in practice. If one CPU's weakness is eliminated by using a more recent/tweaked compiler, then it's not a weakness.
  • coder543 - Tuesday, July 11, 2017 - link

    Rather, you want to test under practical scenarios. Very few people are going to be running 17.04 on production grade servers, they will run an LTS release, which in this case is 16.04.

    It would be good to have benchmarks from 17.04 as another point of comparison, but given how many things they didn't have time to do just using 16.04, I can understand why they didn't use 17.04.
  • Santoval - Wednesday, July 12, 2017 - link

    A compromise can be found by upgrading Ubuntu 16.04's outdated kernel. Ubuntu LTS releases include support for rolling HWE Stacks, which is a simple meta package for installing newer kernels compiled, modified, tested and packaged by the Ubuntu Kernel Team, and installed directly from the official Ubuntu repositories (not via a Launchpad PPA). With HWE 16.04 LTS can install up to the kernel of 18.04 LTS.

    I also use 16.04 LTS + HWE (it just requires installing the linux-generic-hwe-16.04 package), which currently provides the 4.8 kernel. There is even a "beta" version of HWE (the same package plus an -edge at the end) for installing the 4.10 kernel (aka the kernel of 17.04) earlier, which will normally be released next month.

    I just spotted various 4.10 kernel listings after checking in Synaptic, so they must have been added very recently. After that there are two more scheduled kernel upgrades, as is shown in the following link. Of course HWE upgrades solely the kernel, it does not upgrade any application or any of the user level parts to a more recent version of Ubuntu.
    https://wiki.ubuntu.com/Kernel/RollingLTSEnablemen...
  • CajunArson - Tuesday, July 11, 2017 - link

    Considering the similarities between RyZen and Haswell (that aren't coincidental at all) you are already seeing a highly optimized set of RyZen results.

    But I have no problem seeing RyZen be tested with the newest distros, the only difference being that even Ubuntu 16.04 already has most of the optimizations for RyZen baked in.
  • coder543 - Tuesday, July 11, 2017 - link

    What similarities? They're extremely different architectures. I can't think of any obvious similarities. Between the CCX model, caches being totally different layouts, the infinity fabric, Intel having better AVX-256/512 stuff (IIRC), etc.

    I don't think 16.04 is naturally any more optimized for Ryzen than it is for Skylake-SP.
  • CajunArson - Tuesday, July 11, 2017 - link

    Oh please, at the core level RyZen is a blatant copy-n-paste of Haswell with the only exception being they just omitted half the AVX hardware to make their lives easier.

    It's so obvious that if you followed any of the developer threads for people optimizing for RyZen they say to just use the Haswell compiler optimizations that actually work better than the official RyZen optimization flags.
  • ddriver - Tuesday, July 11, 2017 - link

    Can't tell if this post is funny or sad.
  • CajunArson - Tuesday, July 11, 2017 - link

    It's neither: It's accurate.

    Don't believe me? Look at the differences in performance of the holy 1800X over multiple Linux distros ranging from pretty new (OpenSuse Tumbleweed) to pretty old (Fedora 23 from 2015): http://www.phoronix.com/scan.php?page=article&...

    Nowhere near the variation that we see with Skylake X since Haswell was already a solved problem long before RyZen lauched.
  • coder543 - Tuesday, July 11, 2017 - link

    Right, of course. Ryzen is a copy-and-paste of Haswell.

    Don't make me laugh.

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